HD3SS3220 Datasheet, PDF (31/43 Pages) Texas Instruments – USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

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HD3SS3220
SLLSES1 – DECEMBER 2015
10.1.3 Differential Signal Spacing
To minimize crosstalk in high-speed interface implementations, the spacing between the signal pairs must be a
minimum of 5 times the width of the trace. This spacing is referred to as the 5W rule. A PCB design with a
calculated trace width of 6 mils requires a minimum of 30 mils spacing between high-speed differential pairs.
Also, maintain a minimum keep-out area of 30 mils to any other signal throughout the length of the trace. Where
the high-speed differential pairs abut a clock or a periodic signal, increase this keep-out to a minimum of 50 mils
to ensure proper isolation. For examples of high-speed differential signal spacing, see Figure 14 and Figure 15.
TXn
TXp
RXn
RXp
30
686
50
General Keep-Out
Inter-Pair Keep-Out
68 6
50
High-Speed/Periodic Keep-Out
Figure 14. USB3/SATA/PCIe Differential Signal Spacing (mils)
DP
DM
30
6
8
6
50
General Keep-Out
High-Speed/Periodic Keep-Out
Figure 15. USB2 Differential Signal Spacing (mils)
10.1.4 High-Speed Differential Signal Rules
• Do not place probe or test points on any high-speed differential signal.
• Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power
regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.
• After BGA breakout, keep high-speed differential signals clear of the SoC because high current transients
produced during internal state transitions can be difficult to filter out.
• When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an
adjacent GND layer. TI does not recommend stripline routing of the high-speed differential signals.
• Ensure that high-speed differential signals are routed ≥ 90 mils from the edge of the reference plane.
• Ensure that high-speed differential signals are routed at least 1.5 W (calculated trace-width × 1.5) away from
voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are
voided.
• Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission
lines.
• Maximize differential pair-to-pair spacing when possible.
Copyright © 2015, Texas Instruments Incorporated
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