HD3SS3220 Datasheet, PDF (15/43 Pages) Texas Instruments – USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

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Type-C Current
Default – 500mA for
(USB2.0)
900 mA for (USB3.1)
Mid – 1.5 A
High – 3 A
HD3SS3220
SLLSES1 – DECEMBER 2015
Table 2. Type-C Current Advertisement for GPIO and I²C Modes
GPIO Mode (ADDR pin NC)
I²C Mode (ADDR pin H, L)
UFP (PORT pin L)
DFP (PORT pin H)
UFP
DFP
Detected current mode
provided through
OUT1/OUT2
CURRENT_MODE=L
CURRENT_MODE=M
CURRENT_MODE=H
Detected current mode
provided through I²C
register
Advertisement selected
through writing I²C
register
7.3.6 Accessory Support
HD3SS3220 supports audio and debug accessories in UFP, DFP and DRP mode. Audio and debug accessory
support is provided through reading of I2C registers. Audio accessory is also support through GPIO mode with
INT_N/OUT3 pin (audio accessory has been detected when INT_N/OUT3 is low).
7.3.7 Audio Accessory
Audio accessory mode is supported through two types of adapters. First, the passive audio adapter can be used
to convert the Type-C connector into an audio port. In order to effectively detect the passive audio adapter, the
HD3SS3220 must detect a resistance < R_(a) on both the CC pins.
Secondly, a charge through audio adapter can be used. The primary difference between a passive and charge
through adapter is that the charge through adapter supports supplying 500 mA of current over VBUS. The charge
through adapter contains a receptacle and a plug. The plug shall act as a DFP and supply VBUS when it sees
it’s connected.
When HD3SS3220 is configured in GPIO mode, OUT3 pin shall be used to determine if an Audio Accessory is
connected. When an Audio Accessory is detected, the OUT3 pin is pulled low.
7.3.8 Debug Accessory
Debug is an additional state supported by USB Type-C. The specification does not define a specific user
scenario for this state, but the end user could use debug accessory mode to enter a test state for production
specific to the application. Charge through debug accessory is not supported by HD3SS3220 when in DRP or
UFP mode. The HD3SS3220 when configured as a DFP-only or as a DRP acting as a DFP detects a debug
accessory which presents R_(d) on both CC1 and CC2 pins. The HD3SS3220 sets ACCESSORY_CONNECTED
register to 3'b110 to indicate a UFP debug accessory. The HD3SS3220 when configured as a UFP-only or as a
DRP acting as a UFP detects a debug accessory which presents R_(p) on both CC1 and CC2 pins. The
HD3SS3220 sets ACCESSORY_CONNECTED register to 3b'111 to indicate a DFP debug accessory.
7.3.9 VCONN support for Active Cables
The HD3SS3220 supplies VCONN to active cables when configured in DFP mode or DRP acting as a DFP.
VCONN is provided only when it is determined that the unconnected CC pin is terminated to a resistance, R_(a),
and after a UFP is detected and the attached. SRC state is entered. VCONN is supplied from VDD5 through a
low resistance power FET out to the unconnected CC pin. VCONN is removed when a detach event is detected
and the active cable is removed.
HD3SS3220 provides a current limiting function which will disconnect VCONN when the current being drawn
from a device is above the max allowed for VCONN. When a VCONN fault has occurred, the VCONN flag in the
I²C register is set and HD3SS3220 stops supplying VCONN (switch turns off), until the register flag has been
cleared. If HD3SS3220 is in GPIO mode when a fault occurs, the VCONN switch is turned off and HD3SS3220
will not supply VCONN until a port detach and re-attach occurs.
7.3.10 I²C and GPIO Control
The HD3SS3220 can be configured for I²C or GPIO using the ADDR pin. The ADDR pin is a 3-level control pin.
When the ADDR pin is left floating (NC), the HD3SS3220 is in GPIO mode. When the ADDR pin is pulled High,
the HD3SS3220 is in I²C mode with address bit 6 equal to 1. When the ADDR pin is pulled low, the HD3SS3220
is in I²C mode with address bit 6 equal to 0.
All outputs for HD3SS3220 are open drain configuration.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: HD3SS3220
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