THS4031_16 Datasheet, PDF (30/47 Pages) Texas Instruments – THS403x 100-MHz Low-Noise High-Speed Amplifiers

THS4031, THS4032
SLOS224H – JULY 1999 – REVISED JUNE 2016
General PowerPAD™ Design Considerations (continued)
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DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
A. The thermal pad is electrically isolated from all terminals in the package.
Figure 66. Views of Thermally-Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 67. PowerPAD™ PCB Etch and Via Pattern
1. Prepare the PCB with a top-side etch pattern as shown in Figure 67. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0,3302 mm) in diameter.
They are kept small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS403xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS403xDGN package should connect to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area, which
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and to all the IC terminals.
8. With these preparatory steps in place, the THS403xDGN IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
The actual thermal performance achieved with the THS403xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches
(7,62 cm × 7,62 cm), then the expected thermal coefficient, R_θJA, is about 58.4°C/W. For a given R_θJA, the
maximum power dissipation is calculated by Equation 4:
P_D
=
æ
ç
T_MAX
- T_A
è ^RqJA
ö
÷
ø
where
• P_D = Maximum power dissipation of THS403x IC(watts)
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