LP3923_15 Datasheet, PDF (30/37 Pages) Texas Instruments – Cellular Phone Power Management Unit

LP3923
SNVS567B – APRIL 2010 – REVISED MAY 2013
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• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave
device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop
condition.
Data Read
Data Write
Address Mode⁽¹⁾
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = ‘1’>[Ack]
[Register Data]<Ack or NAck>
… additional reads from subsequent register address possible
<Stop Condition>
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent register address possible
<Stop Condition>
(1) < > Data from master [ ] Data from slave
REGISTER READ AND WRITE DETAIL
Slave Address
Control Register Add.
S
(7 bits)
'0' A
(8 bits)
A
Register Data
(8 bits)
AP
R/W
Data transferred, byte +
Ack
From Slave to Master
From Master to Slave
A - ACKNOWLEDGE (SDA Low)
S - START CONDITION
P - STOP CONDITION
Figure 11. Register Write Format
Slave Address
Control Register Add.
Slave Address
S
(7 bits)
'0' A
(8 bits)
A Sr
(7 bits)
'1' A
Register Data
(8 bits)
A/
NA
P
R/W
From Slave to Master
From Master to Slave
R/W
Data transferred, byte +
Ack/NAck
Direction of the transfer
will change at this point
A - ACKNOWLEDGE (SDA Low)
NA - ACKNOWLEDGE (SDA High)
S - START CONDITION
Sr - REPEATED START CONDITION
P - STOP CONDITION
Figure 12. Register Read Format
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