DRV8886AT Datasheet, PDF (3/40 Pages) Texas Instruments – 2-A Stepper Motor Driver With Integrated Current Sense and AutoTune Technology

www.ti.com
5 Pin Configuration and Functions
PWP PowerPAD™ Package
24-Pin HTSSOP
Top View
DRV8886AT
SLVSDO1 – JANUARY 2017
CPL
1
CPH
2
VCP
3
VM
4
AOUT1
5
PGND
6
AOUT2
7
BOUT2
8
PGND
9
BOUT1
10
VM
11
GND
12
Thermal
Pad
24
DECAY
23
TRQ
22
M1
21
M0
20
DIR
19
STEP
18
ENABLE
17
nSLEEP
16
RREF
15
nFAULT
14
DVDD
13
AVDD
Not to scale
PIN
NAME
NO.
AOUT1
5
AOUT2
7
AVDD
13
BOUT1
10
BOUT2
8
CPH
2
CPL
1
DECAY
24
DIR
20
DVDD
14
ENABLE
18
GND
12
M0
21
M1
22
6
PGND
9
RREF
16
STEP
19
TRQ
23
VCP
3
4
VM
11
nFAULT
15
nSLEEP
17
TYPE ⁽¹⁾
Pin Functions
DESCRIPTION
O
PWR
O
Winding A output. Connect to stepper motor winding.
Internal regulator. Bypass to GND with a X5R or X7R, 0.47-µF, 6.3-V ceramic capacitor.
Winding B output. Connect to stepper motor winding.
PWR
I
I
PWR
I
PWR
I
Charge pump switching node. Connect a X5R or X7R, 0.022-µF, VM-rated ceramic capacitor from CPH to CPL.
Decay-mode setting. Sets the decay mode (see the Decay Modes section). Decay mode is latched on device enable.
Direction input. Logic level sets the direction of stepping; internal pulldown resistor.
Internal regulator. Bypass to GND with a X5R or X7R, 0.47-µF, 6.3-V ceramic capacitor.
Enable driver input. Logic high to enable device outputs; logic low to disable; internal pulldown resistor.
Device ground. Connect to system ground.
Microstepping mode-setting. Sets the step mode; tri-level pins; sets the step mode; internal pulldown resistor.
PWR
I
I
I
PWR
PWR
OD
I
Power ground. Connect to system ground.
Current-limit analog input. Connect resistor to ground to set full-scale regulation current.
Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor.
Current-scaling control. Scales the output current; tri-level pin.
Charge pump output. Connect a X5R or X7R, 0.22-µF, 16-V ceramic capacitor to VM.
Power supply. Connect to motor supply voltage and bypass to GND with two 0.01-µF ceramic capacitors (one for each pin)
plus a bulk capacitor rated for VM.
Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor.
(1) I = input, O = output, PWR = power, OD = open-drain
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8886AT
Submit Documentation Feedback
3