BQ2205LYPWR Datasheet, PDF (3/14 Pages) Texas Instruments – POWER MONITORING AND SWITCHING CONTROLLER FOR 3.3-V SRAM

bq2205LY
ELECTRICAL CHARACTERISTICS
(TA = 25°C, VCC(min) ≤ VCC ≤ VCC(max) unless otherwise noted)
SLUS581 − FEBRUARY 2004
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC supply current, ICC(vcc)
VCC > VCC(MIN)
CE = low
CECONX = 0 mA
210
500
µA
Backup Battery Supply Current, ICC(BC)
VBC > VBC(MIN), VCC = 0 V
CE = low
CECONX = 0 mA
50
150
nA
Output voltage (VOUT)
Power fail detect voltage, VPFD
Supply switch-over voltage, VSO
RST output voltage
I(VOUT) ₌ 80 mA, VCC > V(SO)
I(VOUT)= 100µ A, VCC < V(SO)
VBC > V(PFD)
VBC < V(PFD)
I(RST) = 1 mA
Vcc−0.3
VBC−0.3
2.85
2.9
VPFD
VBC
2.95
V
0.4
BW output voltage
I(BW)= 1 mA
0.4
Input leakage current on A and CE pins
−1
1
µA
Voh CEcon1,2
Vol CEcon1,2
Battery warning level VBW
Capacitance
Ioh = 0.5 mA
Iol = 2.0 mA
(1)
2.4
0.4
V
0.677xVCC
Output capacitance
Input capacitance
VOUT = 0 V
VOUT = 0 V
7
pF
5
Power-Down and Power-Up Timing, Refer to Figure 1 through 3
VCC slew rate fall time, tF
3.0 V to 0.0 V
300
µs
VCC slew rate rise time, tR
VSO to VPFD(max)
100
VPFD to RST active, tRST
(reset active timeout period)
Chip-enable recovery time, tCER
(2)
30
85
ms
30
85
Chip-enable propagation delay time to external
SRAM, tCED
See Figure 2
15
25
ns
Push-button low time, tPBL
RST pin
1
µs
(1) _{Battery warning level is detected on power up and the BW pin is latched at tCER time after VCC passes through VPFD on power up.}
(2) _{Time during which external SRAM is write protected after VCC passes through VPFD on power up.}
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