LM3S317 Datasheet, PDF (291/551 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S317 Microcontroller
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
12
reserved
RO
RO
RO
0
0
0
11
10
9
8
7
CBERIS CBMRIS TBTORIS
RO
RO
RO
RO
RO
0
0
0
0
0
22
21
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RTCRIS CAERIS CAMRIS TATORIS
RO
RO
RO
RO
RO
0
0
0
0
0
Bit/Field
31:11
10
9
8
7:4
3
2
1
0
Name
reserved
CBERIS
CBMRIS
TBTORIS
reserved
RTCRIS
CAERIS
CAMRIS
TATORIS
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0x00
0
0
0
0x0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
July 14, 2014
291
Texas Instruments-Production Data