LM3S317 Datasheet, PDF (213/551 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S317 Microcontroller
6.2.2.4
6.2.2.5
6.2.2.6
6.2.2.7
Read-Only Protection
Read-only protection prevents the contents of the flash block from being re-programmed, while still
allowing the content to be read by processor or the debug interface. Note that if a FMPREn bit is
cleared, all read accesses to the Flash memory block are disallowed, including any data accesses.
Care must be taken not to store required data in a Flash memory block that has the associated
FMPREn bit cleared.
The read-only mode does not prevent read access to the stored program, but it does provide
protection against accidental (or malicious) erasure or programming. Read-only is especially useful
for utilities like the boot loader when the debug interface is permanently disabled. In such
combinations, the boot loader, which provides access control to the Flash memory, is protected
from being erased or modified.
Permanently Disabling Debug
For extremely sensitive applications, the debug interface to the processor and peripherals can be
permanently disabled, blocking all accesses to the device through the JTAG or SWD interfaces.
With the debug interface disabled, it is still possible to perform standard IEEE instructions (such as
boundary scan operations), but access to the processor and peripherals is blocked.
The two most-significant bits of the FMPRE register are the DBG bits, and control whether or not the
debug interface is turned on or off. Since the DBG bits are part of the FMPRE register, the user loses
the capability to mark the upper two flash blocks in a 64 KB flash device as execute-only.
The debug interface should not be permanently disabled without providing some mechanism–-such
as the boot loader–-to provide customer-installable updates or bug fixes. Disabling the debug
interface is permanent and cannot be reversed.
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 222) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 221).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 223).
Flash Memory Protection by Disabling Debug Access
Flash memory may also be protected by permanently disabling access to the Debug Access Port
(DAP) through the JTAG and SWD interfaces. Access is disabled by clearing the DBG field of the
FMPRE register.
If the DBG field in the Flash Memory Protection Read Enable (FMPRE) register is programmed
to 0x2, access to the DAP is enabled through the JTAG and SWD interfaces. If clear, access to the
DAP is disabled. The DBG field programming becomes permanent and irreversible after a commit
sequence is performed.
July 14, 2014
213
Texas Instruments-Production Data