OPA189 Datasheet, PDF (29/34 Pages) Texas Instruments – Precision, 36-V, 14-MHz, MUX-Friendly Low-Noise, Rail-to-Rail Output, Zero-Drift Operational Amplifiers

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12 Layout
OPA189, OPA2189, OPA4189
SBOS830 – JUNE 2017
12.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information, see The PCB is a component of op amp design'.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
as opposed to in parallel with the noisy trace.
• Place the external components as close as possible to the device. As illustrated in Figure 20, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• For best performance, TI recommends cleaning the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
12.2 Layout Example
R1
IN±
IN+
R2
R4
R3
1 NC
2 ±IN ±
3 +IN +
4 V±
NC 8
V+ 7
OUT 6
NC 5
+V
C3
C4
OUT
-V
C1
C2
Place bypass
capacitors as close to
device as possible
Use ground pours for
GND
shielding the input
(avoid use of vias)
C3
C4
signal pairs
IN±
R1
R2
IN+
GND
Place components
C1
close to device and to
each other to reduce
parasitic errors
C2
R3
1 NC
2 ±IN
3 +IN
4 V±
NC 8
V+ 7
OUT 6
NC 5
+V
OUT
R4
-V
Use a low-
ESR,ceramic bypass
capacitor
Copyright © 2017, Texas Instruments Incorporated
Figure 20. Operational Amplifier Board Layout for Difference Amplifier Configuration
Copyright © 2017, Texas Instruments Incorporated
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Product Folder Links: OPA189 OPA2189 OPA4189