DAC8562 Datasheet, PDF (29/56 Pages) Analog Devices – +5 Volt, Parallel Input Complete 12-Bit DAC

www.ti.com
POWER-ON RESET
DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719C – AUGUST 2010 – REVISED JUNE 2011
Power-On Reset to Zero-scale
The DAC7562, DAC8162, and DAC8562 contain a power-on-reset circuit that controls the output voltage during
power up. All device registers are reset as shown in Table 6. At power up all DAC registers are filled with zeros
and the output voltages of all DAC channels are set to zero volts. Each DAC channel remains that way until a
valid load command is written to it. The power-on reset is useful in applications where it is important to know the
state of the output of each DAC while the device is in the process of powering up. No device pin should be
brought high before power is applied to the device. The internal reference is disabled by default and remains that
way until a valid reference-change command is executed.
Power-On Reset to Mid-scale
The DAC7563, DAC8163, and DAC8563 contain a power-on reset circuit that controls the output voltage during
power up. At power up, all DAC registers are reset to mid-scale code and the output voltages of all DAC
channels are set to V_REFIN/2 volts. Each DAC channel remains that way until a valid load command is written to
it. The power-on reset is useful in applications where it is important to know the state of the output of each DAC
while the device is in the process of powering up. No device pin should be brought high before power is applied
to the device. The internal reference is powered off/down by default and remains that way until a valid
reference-change command is executed. If using an external reference, it is acceptable to power on the V_REFIN
either at the same time as or after AV_DD is applied.
Table 6. DACxx62 and DACxx63 Power-On Reset Values
REGISTER
DAC and Input registers
LDAC registers
Power-down registers
Internal reference register
Gain registers
DEFAULT SETTING
DACxx62
Zero-scale
DACxx63
Mid-scale
LDAC pin enabled for both channels
DACs powered up
Internal reference disabled
Gain = 1 for both channels
CLR FUNCTIONALITY
The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 7.
When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output
voltages accordingly. The part exits clear mode on the 24^th falling edge of the next write to the part. If the CLR
pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and
changes the input and DAC registers immediately according to Table 7.
Table 7. Clear Mode Reset Values
DEVICE
DAC8562, DAC8162, DAC7562
DAC8563, DAC8163, DAC7563
DAC Output Entering Clear Mode
Zero-scale
Mid-scale
Copyright © 2010–2011, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563