DAC8562 Datasheet, PDF (16/56 Pages) Analog Devices – +5 Volt, Parallel Input Complete 12-Bit DAC

DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719C – AUGUST 2010 – REVISED JUNE 2011
TYPICAL CHARACTERISTICS: DAC at AV_DD = 5.5 V (continued)
At T_A = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
FULL-SCALE SETTLING TIME:
FULL-SCALE SETTLING TIME:
RISING EDGE
FALLING EDGE
LDAC Trigger (5 V/div)
LDAC Trigger (5 V/div)
Large Signal V_OUT (2 V/div)
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Small Signal Settling
(1.22 mV/div = 0.024% FSR)
Large Signal V_OUT (2 V/div)
Small Signal Settling (1.22 mV/div = 0.024% FSR)
Time (5 μs/div)
Figure 31.
From Code: 0h
To Code: FFFFh
HALF-SCALE SETTLING TIME:
RISING EDGE
LDAC Trigger (5 V/div)
Time (5 μs/div)
Figure 32.
From Code: FFFFh
To Code: 0h
HALF-SCALE SETTLING TIME:
FALLING EDGE
LDAC Trigger (5 V/div)
Large Signal V_OUT (2 V/div)
Large Signal V_OUT (2 V/div)
Small Signal Settling (1.22 mV/div = 0.024% FSR)
Small Signal Settling (1.22 mV/div = 0.024% FSR)
Time (5 μs/div)
Figure 33.
From Code: 4000h
To Code: C000h
POWER-ON GLITCH
RESET TO ZERO SCALE
AV_DD (2 V/div)
V_OUTA (50 mV/div)
V_OUTB (50 mV/div)
V_REFIN shorted to AV_DD
Time (1 ms/div)
Figure 35.
Time (5 μs/div)
Figure 34.
From Code: C000h
To Code: 4000h
POWER-ON GLITCH
RESET TO MIDSCALE
AV_DD (2 V/div)
V_OUTA (1 V/div)
V_OUTB (1 V/div)
V_REFIN shorted to AV_DD
Time (1 ms/div)
Figure 36.
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