ADS61JB46 Datasheet, PDF (29/48 Pages) Texas Instruments – 14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Output Interface

ADS61JB46
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REGISTER BIT NAME
FLIP_ADC_BUS
TESTMODE_EN
S_IDLE
S_TEST0
S_TEST1
CTRL_F
CTRL_K
S_SCR
F[7:0]
K[4:0]
CML_I[3:0]
FORCE_OUT_LANE1
OUT_WORD_LANE1[9:0]
FORCE_OUT_LANE2
OUT_WORD_LANE2[9:0]
EN_SIG_EST
EN_PWR_EST
SAMPLES_PWR_EST[2:0]
BIT LOCATION
ADDRESS
(Hex)
BIT
A0
3
A0
4
A0
5
A0
6
A0
7
A1
0
A1
1
A5
7
A6
7:0
A7
4:0
B0
3:0
B4
3
B6
7:0
B7
7:6
B4
6
B8
7:4
B9
7:2
D6
0
D6
5
D6
4:2
SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013
DESCRIPTION
By default, the last octet in the frame is derived from the data octet on the LSB side. The
occurrence of consecutive last octets may be rare because the LSB octets usually
switch more (frame-to-frame) than the MSB octets. This condition can lead to an
infrequent occurrence of frame alignment symbols. To increase the rate of consecutive
last octets (and thereby the rate of frame and multiframe alignment symbols), this bit can
be set to '1'.
Setting this bit to '1' flips the bit order of the ADC inputs (N bits) to the JESD204A logic.
Note that the two zeros padded at the end to cause the JESD204A logic input to remain
unchanged.
This bit enables the transmission of the test sequence mentioned in the JESD204A
document.
Software idle generation control.
Normally the output during code group synchronization is K28.5. When S_IDLE is set to
'1', the device output is a K28.5 comma followed by either a D5.6 or a D16.2 alignment
symbol. This configuration is as per IEEE standard 802.3-2002 (part 3, clause 36.2.4.12)
and enables compatibility with TI’s TLK family of devices.
This bit control is similar to the IDLE pin control (see Table 6).
These two bit controls are similar to the TEST1 and TEST0 pin controls.
This bit enables writes into register A6h, bits 7:0.
This bit enables writes into register A7h, bits 4:0.
Software scrambling enable. This bit control is similar to the SCR pin control.
These bits control the number of octets per frame.
Default is set to 00000001 (2 – 1), which is two octets per frame (single-lane mode). For
a two-lane output (one octet per frame), set these bits to 00000000.
Note that in order to override default, CTRL_F must be set to '1'.
These bits control the number of frames per each multiframe (minus 1). Default depends
on value of bits F[7:0].
When F = 0 (10x mode), K = 16 (17 frames per multiframe)
When F = 1 (20x mode), K = 8 (nine frames per multiframe)
Note that to override the default value of bits K[4:0], CTRL_K must be set to '1'. When
CTRL_K is set to '1', the value programmed in bits A7[4:0] denotes the number of
frames per multiframe (minus 1). For example, to set the number of frames per
multiframe to 23, set CTRL_K = 1 and A7[4:0] = 10110.
CML buffer current select. Default (0000) is 16 mA.
Current is calculated as: 16 mA +16 mA × bit 3 – 8 mA × bit 2 – 4 mA × bit 1 – 2 mA ×
bit 0
This bit replaces the output of the 8b/10b coder (corresponding to the MSB octet) with a
10-bit word specified in the OUT_WORD_LANE1[9:0] bits.
These bits are a 10-bit word replacing the output of the 8b/10b coder when
FORCE_OUT_LANE1 is set to ‘1’.
This bit replaces the output of the 8b/10b coder (corresponding to the LSB octet) with a
10-bit word specified in the OUT_WORD_LANE2[9:0] bits.
These bits are a 10-bit word replacing the output of the 8b/10b coder when
FORCE_OUT_LANE2 is set to ‘1’.
This bit outputs a 4-bit ADC code with low latency on the DETECT[3:0] bits.
This bit outputs a 4-bit average power estimate of the input signal on the DETECT[3:0]
bits.
Power estimate is in dB scale in steps of approximately 1 dB. Refer to the Signal Power
Estimation section.
These bits determine the number of samples to average for power estimation.
These bits are programmable from 1K to 16K.
Copyright © 2013, Texas Instruments Incorporated
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