ADS61JB46 Datasheet, PDF (20/48 Pages) Texas Instruments – 14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Output Interface

ADS61JB46
SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S = 153.6 MSPS, sine-wave input clock,
1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-
point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.
77.5
78
45
Input Frequency = 20MHz
SNR
77
THD _77.5
40
76.5
77
35
76
76.5
30
75.5
76
75
75.5
25
74.5
75
20
74
74.5
15
73.5
74
10
73
73.5
5
72.5
73
20
30
40
50
60
70
80
0
Input Clock Duty Cycle (%)
G025
Figure 32. PERFORMANCE vs
INPUT CLOCK DUTY CYCLE
Output Codes (LSB)
G026
Figure 33. OUTPUT CODES HISTOGRAM WITH IDLE
CHANNEL INPUT
0
0
f_IN = 20 MHz
SFDR = 75 dBc
f_PSRR = 10 MHz
−20
50 − mV_PP
−20
Amplitude(f_IN) = −1 dBFS
Amplitude(f_PSRR) = −104 dBFS
−40
Amplitude(f_IN + f_PSRR) = −96 dBFS
Amplitude(f_IN − f_PSRR) = −98 dBFS
−40
f_IN = 20 MHz
SFDR = 74 dBc
f_CM = 10 MHz
50 − mV_PP
Amplitude(f_IN) = −1 dBFS
Amplitude(f_CM) = −94.6 dBFS
Amplitude(f_IN + f_CM) = −88 dBFS
Amplitude(f_IN − f_CM) = −89 dBFS
−60
−60
−80
−80
−100
−100
−120
0
15
30
45
60
75
Frequency (MHz)
G054
Figure 34. POWER-SUPPLY REJECTION RATIO SPECTRUM
FOR AVDD SUPPLY
−120
0
15
30
45
60
75
Frequency (MHz)
G055
Figure 35. COMMON-MODE REJECTION RATIO SPECTRUM
FOR AVDD SUPPLY
20
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