LP3952 Datasheet, PDF (28/46 Pages) National Semiconductor (TI) – 6-Channel Color LED Driver with Audio Synchronization

LP3952
SNVS518A – JULY 2007 – REVISED MARCH 2013
ack from slave
ack from slave repeated start
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ack from slave data from slave ack from master
start
msb Chip Address lsb w
msb Register Add lsb
rs msb Chip Address lsb r
msb DATA lsb
stop
SCL
SDA
start
Id = 54h
w ack
addr = h00
ack rs
Id = 54h
Figure 18. I²C Read Cycle
r ack Address 00h data ack stop
SDA
8
SCL
1
7
6
2
8
1
5
3
4
Figure 19. I²C Timing Diagram
10
7
9
I²C Timing Parameters
V_DD1,2 = 3.0 to 4.5V, V_{DD_IO} = 1.65V to V_DD1,2
Symbol
1
2
3
4
5
5
6
7
8
9
10
C_b
Parameter
Hold Time (repeated) START Condition
Clock Low Time
Clock High Time
Setup Time for a Repeated START Condition
Data Hold Time (Output direction, delay generated by LP3952)
Data Hold Time (Input direction, delay generated by the Master)
Data Setup Time
Rise Time of SDA and SCL
Fall Time of SDA and SCL
Set-up Time for STOP condition
Bus Free Time between a STOP and a START Condition
Capacitive Load for Each Bus Line
Limit
Min
Max
0.6
1.3
600
600
300
900
0
900
100
20+0.1C_b
300
15+0.1C_b
300
600
1.3
10
200
Units
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
μs
pF
28
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