LP3952 Datasheet, PDF (27/46 Pages) National Semiconductor (TI) – 6-Channel Color LED Driver with Audio Synchronization

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LP3952
SNVS518A – JULY 2007 – REVISED MARCH 2013
SDA
SCL
S
START condition
P
STOP condition
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9^th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3952 address is 54h or 55H as selected with ADDR_SEL
pin. I²C address for LP3952 is 54H when ADDR_SEL=0 and 55H when ADDR_SEL=1. For the eighth bit, a
“0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be
written. The third byte contains data to write to the selected register.
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
Bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
I²C SLAVE address (chip address)
Figure 16. I²C Chip Address
Register changes take an effect at the SCL rising edge during the last ACK from slave.
ack from slave
ack from slave
ack from slave
start
msb Chip Address lsb w ack msb Register Add lsb ack
msb DATA lsb
ack stop
SCL
SDA
start
Id = 54h
w ack
addr = 02h
ack
address 02h data
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 54H (ADDR_SEL=0) or 55H (ADDR_SEL=1) for LP3952.
Figure 17. I²C Write Cycle
ack stop
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform.
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