LP3952 Datasheet, PDF (23/46 Pages) National Semiconductor (TI) – 6-Channel Color LED Driver with Audio Synchronization

LP3952
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SNVS518A – JULY 2007 – REVISED MARCH 2013
Blinking ON/OFF cycle is defined so that there will be first OFF-period then ON-period after which follows an off-
period for the remaining cycle time that can not be set. If OFF and ON times are together more than 100% the
first OFF time will be as set and the ON time is cut to meet 100%. For example, if 50% OFF time is set and ON
time is set greater than 50%, only 50% ON time is used, the exceeding ON time is ignored. If OFF and ON times
are together less than 100% the remaining cycle time output is OFF.
R1 output
OFF ON
10% 10%
Blinking cycle time
Remaining OFF time
100 - 10 - 10 = 80%
OFF ON
10% 10%
G1 output
OFF
20%
ON
20%
100 - 20 - 20 = 60%
OFF
20%
B1 output
R1SW bit
G1SW bit
B1SW bit
OFF
40%
ON
10% ^{100 - 40 - 10 = 50%}
EN_BLINK bit
R1, G1, B1
CYCLE EN bits
Values for setting the blinking cycle for RGB1 can be seen in following table:
Table 3. R1, G1 and B1 Cycle Registers (02H, 04H and 06H):(1.65V ≤ V_DDIO ≤ V_DD1,2V) (unless otherwise
noted)
Name
R1_CYCLE_EN
G1_CYCLE_EN
B1_CYCLE_EN
R1_CYCLE[2:0]
G1_CYCLE[2:0]
B1_CYCLE[2:0]
Bit
Decription
3
Blinking enable
0 = disabled
1 = enabled, output state is defined with blinking cycle
2-0
RGB1 cycle time
Bits
Blinking cycle time
Blinking frequency
000
0.1s
10 Hz
001
0.25s
4 Hz
010
0.5s
2 Hz
011
1s
1 Hz
100
2s
0.5 Hz
101
3s
0.33 Hz
110
4s
0.25 Hz
111
5s
0.2 Hz
Table 4. PATTERN_GEN_CTRL Register (11H):(1.65V ≤ V_DDIO ≤ V_DD1,2V) (unless otherwise noted)
Name
Bit
Description
EN_BLINK
3
Blinking sequence start bit
0 = disabled
1 = enabled
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