AM3894_15 Datasheet, PDF (274/313 Pages) Texas Instruments – Sitara ARM Microprocessors

AM3894
AM3892
SPRS681G – OCTOBER 2010 – REVISED MARCH 2015
www.ti.com
HEX ADDRESS
0x5100 0074
0x5100 0078
0x5100 007C
0x5100 0100
0x5100 0104
0x5100 0108
0x5100 010C
0x5100 0180
0x5100 0184
0x5100 0188
0x5100 018C
0x5100 01C0
0x5100 01C4
0x5100 01C8
0x5100 01CC
0x5100 01D0
0x5100 01D4
0x5100 01D8
0x5100 01DC
0x5100 0200
0x5100 0204
0x5100 0300
0x5100 0304
0x5100 0308
0x5100 030C
0x5100 0310
0x5100 0314
0x5100 0318
0x5100 031C
0x5100 0320
0x5100 0324
0x5100 0328
0x5100 032C
0x5100 0330
0x5100 0334
0x5100 0338
0x5100 033C
0x5100 0380
0x5100 0384
0x5100 0388
0x5100 0390
0x5100 0394
Table 9-88. PCIe Registers (continued)
ACRONYM
GPR1
GPR2
GPR3
MSI0_IRQ_STATUS_RAW
MSI0_IRQ_STATUS
MSI0_IRQ_ENABLE_SET
MSI0_IRQ_ENABLE_CLR
IRQ_STATUS_RAW
IRQ_STATUS
IRQ_ENABLE_SET
IRQ_ENABLE_CLR
ERR_IRQ_STATUS_RAW
ERR_IRQ_STATUS
ERR_IRQ_ENABLE_SET
ERR_IRQ_ENABLE_CLR
PMRST_IRQ_STATUS_RAW
PMRST_IRQ_STATUS
PMRST_ENABLE_SET
PMRST_ENABLE_CLR
OB_OFFSET_INDEXn
OB_OFFSETn_HI
IB_BAR0
IB_START0_LO
IB_START0_HI
IB_OFFSET0
IB_BAR1
IB_START1_LO
IB_START1_HI
IB_OFFSET1
IB_BAR2
IB_START2_LO
IB_START2_HI
IB_OFFSET2
IB_BAR3
IB_START3_LO
IB_START3_HI
IB_OFFSET3
PCS_CFG0
PCS_CFG1
PCS_STATUS
SERDES_CFG0
SERDES_CFG1
REGISTER NAME
General Purpose 1
General Purpose 2
General Purpose 3
MSI 0 Interrupt Raw Status
MSI 0 Interrupt Enabled Status
MSI 0 Interrupt Enable Set
MSI 0 Interrupt Enable Clear
Raw Interrupt Status
Interrupt Enabled Status
Interrupt Enable Set
Interrupt Enable Clear
Raw ERR Interrupt Status
ERR Interrupt Enabled Status
ERR Interrupt Enable Set
ERR Interrupt Enable Clear
Power Management and Reset Interrupt Status
Power Management and Reset Interrupt Enabled Status
Power Management and Reset Interrupt Enable Set
Power Management and Reset Interrupt Enable Clear
Outbound Translation Region N Offset Low and Index
Outbound Translation Region N Offset High
Inbound Translation Bar Match 0
Inbound Translation 0 Start Address Low
Inbound Translation 0 Start Address High
Inbound Translation 0 Address Offset
Inbound Translation Bar Match 1
Inbound Translation 1 Start Address Low
Inbound Translation 1 Start Address High
Inbound Translation 1 Address Offset
Inbound Translation Bar Match 2
Inbound Translation 2 Start Address Low
Inbound Translation 2 Start Address High
Inbound Translation 2 Address Offset
Inbound Translation Bar Match 3
Inbound Translation 3 Start Address Low
Inbound Translation 3 Start Address High
Inbound Translation 3 Address Offset
PCS Configuration 0
PCS Configuration 1
PCS Status
SerDes Configuration for Lane 0
SerDes Configuration for Lane 1
274 Peripheral Information and Timings
Copyright © 2010–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM3894 AM3892