AM3894_15 Datasheet, PDF (1/313 Pages) Texas Instruments – Sitara ARM Microprocessors

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AM3894
AM3892
SPRS681G – OCTOBER 2010 – REVISED MARCH 2015
AM389x Sitara™
ARM^® Microprocessors (MPUs)
1 Device Overview
1.1 Features
1
• High-Performance Sitara ARM^® Microprocessors
(MPUs)
– ARM Cortex™-A8 RISC Processor
• Up to 1.20 GHz
• ARM Cortex-A8 Core
– ARMv7 Architecture
• In-Order, Dual-Issue, Superscalar Processor
Core
• NEON™ Multimedia Architecture
– Supports Integer and Floating Point (VFPv3-
IEEE754 Compliant)
• Jazelle^® RCT Execution Environment
• ARM Cortex-A8 Memory Architecture
– 32-KB Instruction and Data Caches
– 256-KB L2 Cache
– 64-KB RAM, 48-KB of Boot ROM
• 512KB of On-Chip Memory Controller (OCMC)
RAM
• SGX530 3D Graphics Engine (Available Only on
the AM3894 Device)
– Delivers up to 30 MTriangles per Second
– Universal Scalable Shader Engine
– Direct3D^® Mobile, OpenGL^® ES 1.1 and 2.0,
OpenVG™ 1.1, OpenMax™ API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
• Endianness
– ARM Instructions and Data – Little Endian
• HD Video Processing Subsystem (HDVPSS)
– Two 165-MHz HD Video Capture Channels
• One 16-Bit or 24-Bit and One 16-Bit Channel
• Each Channel Splittable Into Dual 8-Bit
Capture Channels
– Two 165-MHz HD Video Display Channels
• One 16-Bit, 24-Bit, 30-Bit Channel and One
16-Bit Channel
– Simultaneous SD and HD Analog Output
– Digital HDMI 1.3 Transmitter with PHY with
HDCP up to 165-MHz Pixel Clock
– Three Graphics Layers
• Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
– Supports up to DDR2-800 and DDR3-1600
– Up to Eight x8 Devices Total
– 2GB of Total Address Space
1
– Dynamic Memory Manager (DMM)
• Programmable Multi-Zone Memory Mapping
and Interleaving
• Enables Efficient 2D Block Accesses
• Supports Tiled Objects in 0°, 90°, 180°, or
270° Orientation and Mirroring
• Optimizes Interlaced Accesses
• One PCI Express^® (PCIe) 2.0 Port with Integrated
PHY
– Single Port with 1 or 2 Lanes at 5.0 GT per
Second
– Configurable as Root Complex or Endpoint
• Serial ATA (SATA) 3.0 Gbps Controller with
Integrated PHYs
– Direct Interface for Two Hard Disk Drives
– Hardware-Assisted Native Command Queuing
(NCQ) from up to 32 Entries
– Supports Port Multiplier and Command-Based
Switching
• Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet
MACs (EMAC)
– IEEE 802.3 Compliant (3.3-V I/O Only)
– MII and GMII Media Independent Interfaces
– Management Data I/O (MDIO) Module
• Dual USB 2.0 Ports with Integrated PHYs
– USB 2.0 High-Speed and Full-Speed Client
– USB 2.0 High-Speed, Full-Speed, and Low-
Speed Host
– Supports Endpoints 0-15
• General-Purpose Memory Controller (GPMC)
– 8-Bit and 16-Bit Multiplexed Address and Data
Bus
– Up to 6 Chip Selects with up to 256-MB Address
Space per Chip Select Pin
– Glueless Interface to NOR Flash, NAND Flash
(with BCH and Hamming Error Code Detection),
SRAM and Pseudo-SRAM
– Error Locator Module (ELM) Outside of GPMC
to Provide up to 16-Bit and 512-Byte Hardware
ECC for NAND
– Flexible Asynchronous Protocol Control for
Interface to FPGA, CPLD, ASICs
• Enhanced Direct-Memory-Access (EDMA)
Controller
– Four Transfer Controllers
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.