THS1040_15 Datasheet, PDF (27/33 Pages) Texas Instruments – CMOS ANALOG-TO-DIGITAL CONVERTER

Not Recommended For New Designs
THS1040
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
supply decoupling
The analog (AV_DD, AGND) and digital (DV_DD, DGND) power supplies to the THS1040 must be separately
decoupled for best performance. Each supply needs at least a 10-µF electrolytic or tantalum capacitor (as a
charge reservoir) and a 100-nF ceramic type capacitor placed as close as possible to the respective pins (to
suppress spikes and supply noise).
digital output loading and circuit board layout
The THS1040 outputs are capable of driving rail-to-rail with up to 10 pF of load per pin at 40-MHz clock frequency
and 3-V digital supply. Minimizing the load on the outputs improves THS1040 signal-to-noise performance by
reducing the switching noise coupling from the THS1040 output buffers to the internal analog circuits. The
output load capacitance can be minimized by buffering the THS1040 digital outputs with a low input capacitance
buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks
between the THS1040 and this buffer. Inserting small resistors in the range 100 Ω to 300 Ω between the
THS1040 I/O outputs and their loads can help minimize the output-related noise in noise-critical applications.
Noise levels at the output buffers, which may affect the analog circuits within THS1040, increase with the digital
supply voltage. Where possible, consider using the lowest DV_DD that the application can tolerate.
Use good layout practices when designing the application PCB to ensure that any off-chip return currents from
the THS1040 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any
sensitive analog circuits. The THS1040 should be soldered directly to the PCB for best performance. Socketing
the device degrades performance by adding parasitic socket inductance and capacitance to all pins.
user tips for obtaining best performance from the THS1040
D Choose differential input mode for best distortion performance.
D Choose a 2-V ADC input span for best noise performance.
D Choose a 1-V ADC input span for best distortion performance.
D Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short
PCB traces.
D Use a small RC filter (typically 20 Ω and 20 pF) between the signal source(s) the AIN+ (and AIN−) input(s)
when the systems bandwidth requirements allow this.
www.ti.com
27