THS1040_15 Datasheet, PDF (21/33 Pages) Texas Instruments – CMOS ANALOG-TO-DIGITAL CONVERTER

Not Recommended For New Designs
THS1040
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
VBG
+
_
ADC
References
Buffer A2
MODE =
+
AVDD
2
or AVDD
VREF = External
_
REFSENSE
AVDD
Figure 28. Drive VREF Mode
AGND
operating configuration examples
Figure 29 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AV_DD/2 then sets the REFT and
REFB voltages via the internal reference generator for a 2-V_p-p ADC input range. The VREF pin provides the
1-V mid-scale bias voltage required at AIN−. VREF should be well decoupled to AGND to prevent
sample-and-hold switching at AIN− from corrupting the VREF voltage.
2V
20 Ω
AVDD/2
1V
AIN+
0V
20 pF
MODE
20 Ω
20 pF
AIN−
10 µF
0.1 µF
10 µF 0.1 µF
0.1 µF
VREF = 1 V
REFT
REFSENSE
REFB
Figure 29. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
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