THS1040_15 Datasheet, PDF (22/33 Pages) Texas Instruments – CMOS ANALOG-TO-DIGITAL CONVERTER

THS1040
Not Recommended For New Designs
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 30 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input
with 1.5-V_p-p span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap
reference output at VREF to 0.75 V. Tying MODE to AV_DD then sets the REFT and REFB voltages via the internal
reference generator for a 1.5-V_p-p ADC input range.
If a transformer is used to generate the differential ADC input from a single-ended signal, then the BIASREF
pin provides a suitable bias voltage for the secondary windings center tap when MODE = AV_DD.
1.875 V
1.5 V
1.125 V
1.875 V
1.5 V
1.125 V
20 Ω
20 Ω
AIN+
AVDD
MODE
20 pF
AIN−
20 pF
VREF = 0.75 V
0.1 µF
10 µF
0.1 µF
REFSENSE
REFT
0.1 µF
REFB
5 kΩ
10 µF
10 kΩ
Figure 30. Operating Configuration: 1.5-V Differential Input, Internal ADC References
Figure 31 shows a configuration using the internal ADC references and an external VREF source for digitizing
a dc-coupled single-ended input with span 0.5 V to 2 V. A 1.25-V external source provides the bias voltage for
the AIN− pin and also, via a buffered potential divider, the 0.75 VREF voltage required to set the input range
to 1.5 V_p-p MODE is tied to AV_DD to set internal ADC references configuration.
2V
1.25 V
0.5 V
20 Ω
20 pF
AIN+
MODE
AVDD
1.25
Source
20 Ω 20 pF
10 kΩ
_
10 µF (0.75 V)
+
15 kΩ
AIN−
VREF
REFT
REFB
REFSENSE
0.1 µF
0.1 µF 10 µF
0.1 µF
AVDD
Figure 31. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source
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