LMK01801 Datasheet, PDF (27/39 Pages) Texas Instruments – Dual Clock Divider Buffer

16.4 REGISTER R0
The R0 register controls reset, global power down, the power
down functions for the channel dividers and their correspond-
ing outputs, CLKinX divider value and CLKinX divide select.
The X, Y in CLKoutX_Y_PD denote the actually clock output
which may be from 0 to 13 where X is the first CLKout and Y
is the last CLKout.
16.4.1 RESET
Setting this bit will cause the silicon default values to be set
upon loading of R0 by a high LEuWire pin. When program-
ming register R0 with the RESET bit set, all other pro-
grammed values are ignored.
The RESET bit is automatically cleared upon writing any other
register. For instance, when R0 is written to again with default
values.
If the user reprograms the R0, after the initial programming
then set RESET = 0.
R0[4]
0
1
RESET
State
Normal operation
Reset (automatically cleared)
16.4.2 POWERDOWN
Setting this bit causes the device to enter powerdown mode.
Normal operation is resumed by clearing this bit with MI-
CROWIRE. All other MICROWIRE settings are preserved
during POWERDOWN.
R1[5]
0
1
POWERDOWN
State
Normal operation
Powerdown
16.4.3 CLKoutX_Y_PD
This bit powers down the clock outputs as specified by CLK-
outX to CLKoutY. This includes the divider and output buffers.
CLKoutX_Y_PD Programming Addresses
CLKoutX_Y_PD
Programming Address
CLKout0_3_PD
R0[6]
CLKout4_7_PD
R0[7]
CLKout8_11_PD
R0[8]
CLKout12_13_PD
R0[9]
CLKoutX_Y_PD
R0[6,7,8,9]
State
0
Power up clock group
1
Power down clock group
16.4.3.1 CLKinX_BUF_TYPE
There are two input buffer types for CLKin0 and CLKin1: bipo-
lar or CMOS. Bipolar is recommended for differential inputs
such as LVDS and LVPECL. CMOS is recommended for DC
coupled single ended inputs.
When using bipolar, CLKinX and CLKinX* input pins must be
AC coupled when using differential or single ended input.
When using CMOS, CLKinX and CLKinX* input pins may be
AC or DC coupled with a differential input.
When using CMOS in a single ended mode, the used clock
input pin (CLKinX or CLKinX*) may be AC or DC coupled to
the signal source. The unused CLKin shouLd be AC coupled
to ground.
The programming address table shows at what register the
specified CLKinX_BUF_TYPE is located.
The CLKinX_BUF_TYPE table shows the programming def-
inition for these registers.
CLKinX_BUF_TYPE Programming Addresses
CLKinX_BUF_TYPE
Programming Address
CLKin0_BUF_TYPE
R0[10]
CLKin1_BUF_TYPE
R0[11]
R0[10]
0
1
CLKinX_BUF_TYPE
CLKinX Buffer Type
Bipolar
CMOS
16.4.3.2 CLKinX_DIV
These set the CLKin divide value, from 2-8.
CLKinX_DIV Programming Address
CLKinX_DIV
Programming Address
CLKin0_DIV
R0[16:14]
CLKin1_DIV
R0[21:19]
CLKinX_DIV
R0[21:19, 16:14]
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
Divide Value
8
2
2
3
4
5
6
7
16.4.3.3 CLKinX_MUX
These bits select whether or not the CLKin divider is bypassed
or enabled.
CLKinX_MUX Programming Address
CLKinX_MUX
Programming Address
CLKin0_MUX
R0[18:17]
CLKin1_MUX
R0[23:22]
CLKinX_MUX
R0[23:22, 18:17]
0 (0x00)
1(0x01)
State
Bypass
Divide
16.5 REGISTER R1 AND R2
Registers R1 and R2 set the clock output types.
16.5.1 CLKoutX_TYPE
The clock output types of the LMK01801 are individually pro-
grammable. The CLKoutX_TYPE registers set the output
type of an individual clock output to LVDS, LVPECL, LVC-
MOS, or powers down the output buffer. Note that LVPECL
supports three different amplitude levels and LVCMOS sup-
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