LMK01801 Datasheet, PDF (21/39 Pages) Texas Instruments – Dual Clock Divider Buffer

outputs to turn off and then back on with a fixed delay with
respect to the falling edge of the qualification clock. This al-
lows for dynamic adjustments of digital delay with respect to
an output clock.
The qualified SYNC timing is shown in Figure 6 for relative
dynamic digital delay.
Dynamic Digital Delay Conditions
To perform a dynamic digital delay adjustment, the analog
delay must be bypassed by setting CLKout12_ADLY_SEL to
0. If the analog delay is not bypassed the output synchro-
nization may be inaccurate due to unknown analog delay
settings.
When adjusting digital delay dynamically, the falling edge of
the qualifying clock must coincide with the falling edge of the
clock distribution path. For this requirement to be met, pro-
gram the CLKout12_13_HS value of the qualifying clock
group according to Table 7.
TABLE 7. Half Step programming requirement of
qualifying clock during SYNC event
CLKout12_13_DIV value
CLKout12_13_HS
Odd
Must = 1 during SYNC event.
Even
Must = 0 during SYNC event.
15.6.1.1 RELATIVE DYNAMIC DIGITAL DELAY
Relative dynamic digital delay can be used to program a clock
output to a specific phase offset from another clock output.
Pros:
• Direct phase adjustment with respect to same clock
output.
• Possible glitch pulses from clock output will always be the
same during digital delay adjustment transient.
Cons:
• For some clock divide values there may be a glitch pulse
due to SYNC assertion.
• Adjustments of digital delay requiring the half step bit
(CLKout12_13_HS) for finer digital delay adjust is
complicated due to the half step requirement in Table 7
above.
15.6.1.2 RELATIVE DYNAMIC DIGITAL DELAY -
EXAMPLE
To illustrate the relative dynamic digital delay adjust proce-
dure, consider the following example.
System Requirements:
• CLKin1 Frequency = 983.04 MHz
• CLKout8 = 983.04 MHz (CLKout8_11_DIV = 1)
• CLKout12 = 491.52 MHz (CLKout12_13_DIV = 2)
• During initial programming:
— CLKout12_13_DDLY = 5
— CLKout12_13_HS = 0
— NO_SYNC_CLKoutX_Y = 0
The application requires the 491.52 MHz clock to be stepped
in 90 degree steps (~508.6 ps), which is the minimum step
resolution allowable by the clock distribution path. That is 1 /
983.04 MHz / 2 = ~169.5 ps. During the stepping of the 491.52
MHz clocks the 983.04 MHz clock must not be interrupted.
Step 1: The device is programmed from register R0 to R5 with
values that result in the device operating as desired, see the
system requirements above. The phase of all the output
clocks are aligned because all the digital delay and half step
values were the same when the SYNC was generated by
programming register R5. The timing of this is as shown in
Figure 4.
Step 2: Now the registers will be programmed to prepare for
changing digital delay (or phase) dynamically.
Register
Purpose
Use clock output for
SYNC1_QUAL = 3
qualifying the SYNC pulse for
dynamically adjusting digital
delay.
Clock output 8 (983.04 MHz)
NO_SYNC_CLKout7_11 = 1
won't be affected by SYNC. It
will operate without
interruption.
Automatically generation of
SYNC is not allowed
because of the half step
SYNC1_AUTO = 0 (default)
requirement.
SYNC must be generated
manually by toggling the
SYNC_POL_INV bit or the
SYNC pin.
After the above registers have been programmed, the appli-
cation may now dynamically adjust the digital delay of the
491.52 MHz clocks.
Step 3: Adjust digital delay of CLKout12 by one step.
Refer to Table 8 for the programming sequence to step one
half clock distribution period forward or backwards.
TABLE 8. Programming sequence for one step adjust
Step direction and current Programming Sequence
HS state
Adjust clock output one step 1. CLKout12_13_HS = 1.
forward.
CLKout12_13_HS = 0.
Adjust clock output one step 1. CLKout12_13_DDLY = 9.
forward.
2. Perform SYNC event.
CLKout12_13_HS = 1.
3. CLKout12_13_HS = 0.
Adjust clock output one step 1. CLKout12_13_HS = 1.
backward.
2. CLKout12_13_DDLY = 5.
CLKout12_13_HS = 0.
3. Perform SYNC event.
Adjust clock output one step 1. CLKout12_13_HS = 0.
backward.
CLKout12_13_HS = 1.
To fulfill the qualifying clock output half step requirement in
Table 7 when dynamically adjusting digital delay, the
CLKout12_13_HS bit must be set if CLKout12 or CLKout13
has an odd divide. So before any dynamic digital delay ad-
justment, CLKout12_13_HS must be set because the clock
divide value is odd. To achieve the final required digital delay
adjustment, the CLKout12_13_HS bit may cleared after
SYNC.
If a SYNC is to be generated this can be done by toggling the
SYNC pin or by toggling the SYNC_POL_INV bit. Because of
the internal one shot pulse, no strict timing of the SYNC pin
or SYNC_POL_INV bit is required. After the SYNC event, the
clock output will be at the specified phase. See Figure 6 for a
detailed view of the timing diagram. The timing diagram criti-
cal points are:
• Time A) SYNC assertion event is registered.
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