LMK01801 Datasheet, PDF (12/39 Pages) Texas Instruments – Dual Clock Divider Buffer

Symbol
Parameter
Conditions
Min
Typ
LVCMOS Clock Outputs (CLKoutX)
f_CLKout
Maximum Clock Frequency
(Note 14, Note 15)
5 pF Load
250
V_OH
Output High Voltage
1 mA Load
V_CC - 0.1
V_OL
Output Low Voltage
1 mA Load
I_OH
Output High Current (Source)
V_CC = 3.3 V, V_O = 1.65 V
28
I_OL
Output Low Current (Sink)
V_CC = 3.3 V, V_O = 1.65 V
28
DUTY_CLK
Output Duty Cycle
V_CC/2 to V_CC/2, F_CLK = 100 MHz, T
45
50
(Note 14)
= 25 °C
T_R
Output Rise Time
20% to 80%, R_L = 50 Ω,
C_L = 5 pF
400
T_F
Output Fall Time
80% to 20%, R_L = 50 Ω,
C_L = 5 pF
400
MICROWIRE Interface Timing
T_ECS
LE to Clock Set Up Time
See MICROWIRE Input Timing
25
T_DCS
Data to Clock Set Up Time
See MICROWIRE Input Timing
25
T_CDH
Clock to Data Hold Time
See MICROWIRE Input Timing
8
T_CWH
Clock Pulse Width High
See MICROWIRE Input Timing
25
T_CWL
Clock Pulse Width Low
See MICROWIRE Input Timing
25
T_CES
Clock to LE Set Up Time
See MICROWIRE Input Timing
25
T_EWH
LE Pulse Width
See MICROWIRE Input Timing
25
T_CR
Falling Clock to Readback Time
See MICROWIRE Readback
Timing
25
Max
Units
MHz
V
0.1
V
mA
mA
55
%
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
Note 10: See applications section Section 13.1 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY for definition of V_ID and V_OD voltages.
Note 11: For Icc for specific part configuration, see applications section Section 17.1.1 Current Consumption for calculating Icc.
Note 12: The minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin
to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended
clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode
noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the
device outputs.
Note 13: Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.
Note 14: Guaranteed by characterization.
Note 15: Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.
Note 16: For LCPECL, the common mode voltage is regulated (VOH=1.6V, VOL=VOH-Vsw, Vcm=(VOH+VOL)/2 ) and is more stable against with PVT (process,
supply, temperature) variations than conventional LVPECL implementations..
Note 17: With proper selection of external emitter resistors, LCPECL can also be used for DC-coupling with devices with low common voltage such as 0.5V or
0,8V etc.
Note 18: Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.
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