LMK01801 Datasheet, PDF (1/39 Pages) Texas Instruments – Dual Clock Divider Buffer

LMK01801
January 16, 2012
Dual Clock Divider Buffer
1.0 General Description
The LMK01801 is a very low noise solution for clocking sys-
tems that require distribution and frequency division of preci-
sion clocks.
The LMK01801 features extremely low residual noise, fre-
quency division, digital and analog delay adjustments, and
fourteen (14) programmable differential outputs: LVPECL,
LVDS and LVCMOS (2 outputs per differential output).
The LMK01801 features two independent inputs that can be
driven differentially (LVDS, LVPECL) or in single-ended mode
(LVCMOS, RF Sinewave). The first input drives output Bank
A consisting of eight (8) outputs. The second input drives out-
put Bank B consisting of six (6) outputs.
2.0 Target Applications
• High performance clock distribution and division
• Wireless infrastructure
• Datacom and telecom clock distribution
• Medical imaging
• Test and measurement
• Military / Aerospace
3.0 Features
■ ^{Pin control mode or MICROWIRE (SPI)}
■ ^{Input and Output Frequency Range 1 kHz to 3.1 GHz}
■ ^{Separate Input for Clock Output Banks A & B.}
■ ^{14 Differential Clock Outputs in Two Banks (A & B)}
— Output Bank A
■ ^{8 Differential, programmable outputs (Up to 8 as}
LVCMOS)
■ ^{Divider Values of 1 to 8, Even and Odd.}
— Output Bank B
■ ^{6 Differential Outputs (or up to 12 as LVCMOS)}
■ ^{Divides values of 1 to 1045 or 1 to 8, even and odd}
■ ^{Analog and Digital Delays}
■ ^{50% duty cycle on all outputs for all divides}
■ ^{Separate Synchronization of Bank A and B.}
■ ^{RMS Additive jitter 50 fs at 800 MHz}
— 50 fs RMS Additive jitter (12 kHz to 20 MHz)
■ ^{Industrial Temperature Range: -40 to 85 °C}
■ ^{3.15 V to 3.45 V operation}
■ ^{Package: 48-pin LLP (7.0 x 7.0 x 0.8 mm)}
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
PLLatinum™ is a trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated 301487 SNAS573
30148701
www.ti.com