AM3892BCYG120 Datasheet, PDF (264/308 Pages) Texas Instruments – AM389x Sitara™ ARM® Processors

AM3894
AM3892
SPRS681E – OCTOBER 2010 – REVISED JULY 2012
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8.13 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• Supports TDM, I2S, and similar formats
• External shift clock or an internal, programmable frequency shift clock for data transfer
• 5KB Tx and Rx buffer
• Supports three interrupt and two DMA requests.
The McBSP module may support two types of data transfer at the system level:
• The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half-cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time. The interface clock
(CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured
accordingly with the external peripheral (activation edge capability) and the type of data transfer
required at the system level.
For more detailed information on the McBSP peripheral, see the McBSP chapter in the AM389x Sitara
ARM Processors Technical Reference Manual (literature number SPRUGX7).
The following sections describe the timing characteristics for applications in normal mode (that is, the
McBSP connected to one peripheral) and TDM applications in multipoint mode.
8.13.1 McBSP Peripheral Register Descriptions
Table 8-80. McBSP Registers⁽¹⁾
HEX ADDRESS
0x4700 0000
0x4700 0008
0x4700 0010
0x4700 0014
0x4700 0018
0x4700 001C
0x4700 0020
0x4700 0024
0x4700 0028
0x4700 002C
0x4700 0030
0x4700 0034
0x4700 0038
0x4700 003C
0x4700 0040
0x4700 0044
0x4700 0048
0x4700 004C
ACRONYM
DRR_REG
DXR_REG
SPCR2_REG
SPCR1_REG
RCR2_REG
RCR1_REG
XCR2_REG
XCR1_REG
SRGR2_REG
SRGR1_REG
MCR2_REG
MCR1_REG
RCERA_REG
RCERB_REG
XCERA_REG
XCERB_REG
PCR_REG
RCERC_REG
REGISTER NAME
McBSP data receive
McBSP data transmit
McBSP serial port control 2
McBSP serial port control 1
McBSP receive control 2
McBSP receive control 1
McBSP transmit control 2
McBSP transmit control 1
McBSP sample rate generator 2
McBSP sample rate generator 1
McBSP multichannel 2
McBSP multichannel 1
McBSP receive channel enable partition A
McBSP receive channel enable partition B
McBSP transmit channel enable partition A
McBSP transmit channel enable partition B
McBSP pin control
McBSP receive channel enable partition C
(1) Note that the McBSP registers are 32-bit aligned.
264 Peripheral Information and Timings
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