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| AM3892BCYG120 Datasheet, PDF (194/308 Pages) Texas Instruments – AM389x Sitara™ ARM® Processors | |||
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AM3894
AM3892
SPRS681E â OCTOBER 2010 â REVISED JULY 2012
www.ti.com
8.4.3.1 JTAG ID (JTAGID) Register Description
Table 8-28. JTAG ID Register(1)
HEX ADDRESS
0x4814 0600
ACRONYM
JTAGID
REGISTER NAME
JTAG Identification Register(2)
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
(2) Read-only. Provides the device 32-bit JTAG ID.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/device ID. For this
device, the JTAG ID register resides at address location 0x4814 0600. The register hex value for the
device depends on the silicon revision being used. For more information, see the AM389x Sitara ARM
Processors Silicon Errata (literature number SPRZ327). For the actual register bit names and their
associated bit field descriptions, see Figure 8-40 and Table 8-29.
31
28 27
VARIANT (4-
bit)
PART NUMBER (16-bit)
R-x
R-1011 1000 0001 1110
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
12 11
MANUFACTURER (11-bit)
R-0000 0010 111
Figure 8-40. JTAG ID Register Description - 0x4814 0600
10
LSB
R-1
Bit
31:28
27:12
11:1
0
Table 8-29. JTAG ID Register Selection Bit Descriptions
Field
Description
VARIANT
Variant (4-bit) value. Device value: The value of this field depends on the silicon revision being used. For
more information, see the AM389x Sitara ARM Processors Silicon Errata (literature number SPRZ327).
PART NUMBER Part Number (16-bit) value. Device value: 0xB81E
MANUFACTURER Manufacturer (11-bit) value. Device value: 0x017
LSB
LSB. This bit is read as a 1 for this device.
8.4.3.2 JTAG Electrical Data/Timing
(see Figure 8-41)
NO.
1 tc(TCK)
1a tw(TCKH)
1b tw(TCKL)
3 tsu(TDI-TCK)
3 tsu(TMS-TCK)
4
th(TCK-TDI)
th(TCK-TMS)
Table 8-30. Timing Requirements for IEEE 1149.1 JTAG
Cycle time, TCK
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high (20% of (tc * 0.5))
Input setup time, TMS valid to TCK high (20% of (tc * 0.5))
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
MIN
51.15
20.46
20.46
5.115
5.115
10
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Table 8-31. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
(see Figure 8-41)
NO.
2 td(TCKL-TDOV)
PARAMETER
Delay time, TCK low to TDO valid
MIN
MAX UNIT
0 23.575(1) ns
(1) (0.5 * tc) - 2
194 Peripheral Information and Timings
Copyright © 2010â2012, Texas Instruments Incorporated
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