AM3892BCYG120 Datasheet, PDF (204/308 Pages) Texas Instruments – AM389x Sitara™ ARM® Processors

AM3894
AM3892
SPRS681E – OCTOBER 2010 – REVISED JULY 2012
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EMAC0 HEX ADDRESS
0x4A10 00A4
0x4A10 00A8
0x4A10 00AC
0x4A10 00B0
0x4A10 00B4
0x4A10 00B8
0x4A10 00BC
0x4A10 0100
0x4A10 0104
0x4A10 0108
0x4A10 010C
0x4A10 0110
0x4A10 0114
0x4A10 0120
0x4A10 0124
0x4A10 0128
0x4A10 012C
0x4A10 0130
0x4A10 0134
0x4A10 0138
0x4A10 013C
0x4A10 0140
0x4A10 0144
0x4A10 0148
0x4A10 014C
0x4A10 0150
0x4A10 0154
0x4A10 0158
0x4A10 015C
0x4A10 0160
0x4A10 0164
0x4A10 0168
0x4A10 016C
0x4A10 0170
0x4A10 0174
0x4A10 01D0
0x4A10 01D4
0x4A10 01D8
0x4A10 01DC
0x4A10 01E0
Table 8-37. EMAC Control Registers (continued)
EMAC1 HEX ADDRESS
0x4A12 00A4
0x4A12 00A8
0x4A12 00AC
0x4A12 00B0
0x4A12 00B4
0x4A12 00B8
0x4A12 00BC
0x4A12 0100
0x4A12 0104
0x4A12 0108
0x4A12 010C
0x4A12 0110
0x4A12 0114
0x4A12 0120
0x4A12 0124
0x4A12 0128
0x4A12 012C
0x4A12 0130
0x4A12 0134
0x4A12 0138
0x4A12 013C
0x4A12 0140
0x4A12 0144
0x4A12 0148
0x4A12 014C
0x4A12 0150
0x4A12 0154
0x4A12 0158
0x4A12 015C
0x4A12 0160
0x4A12 0164
0x4A12 0168
0x4A12 016C
0x4A12 0170
0x4A12 0174
0x4A12 01D0
0x4A12 01D4
0x4A12 01D8
0x4A12 01DC
0x4A12 01E0
ACRONYM
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
RXBUFFEROFFSET
RXFILTERLOWTHRESH
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
REGISTER NAME
Receive Interrupt Status (Masked)
Receive Interrupt Mask Set
Receive Interrupt Mask Clear
MAC Interrupt Status (Unmasked)
MAC Interrupt Status (Masked)
MAC Interrupt Mask Set
MAC Interrupt Mask Clear
Receive
Multicast/Broadcast/Promiscuous
Channel Enable
Receive Unicast Enable Set
Receive Unicast Clear
Receive Maximum Length
Receive Buffer Offset
Receive Filter Low Priority Frame
Threshold
Receive Channel 0 Flow Control
Threshold
Receive Channel 1 Flow Control
Threshold
Receive Channel 2 Flow Control
Threshold
Receive Channel 3 Flow Control
Threshold
Receive Channel 4 Flow Control
Threshold
Receive Channel 5 Flow Control
Threshold
Receive Channel 6 Flow Control
Threshold
Receive Channel 7 Flow Control
Threshold
Receive Channel 0 Free Buffer Count
Receive Channel 1 Free Buffer Count
Receive Channel 2 Free Buffer Count
Receive Channel 3 Free Buffer Count
Receive Channel 4 Free Buffer Count
Receive Channel 5 Free Buffer Count
Receive Channel 6 Free Buffer Count
Receive Channel 7 Free Buffer Count
MAC Control
MAC Status
Emulation Control
FIFO Control
MAC Configuration
Soft Reset
MAC Source Address Low Bytes
MAC Source Address High Bytes
MAC Hash Address 1
MAC Hash Address 2
Back Off Test
204 Peripheral Information and Timings
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