THS1009_14 Datasheet, PDF (26/31 Pages) Texas Instruments – Simultaneous Sampling of Two Single-Ended Signals or One Differential Signals or Combination of Both

THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE
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The THS1009 features two analog input channels. These can be configured for either single-ended or differential
operation. Figure 33 shows a simplified model, where a single-ended configuration for channel AINP is selected. The
reference voltages for the ADC itself are V_REFP and V_REFM (either internal or external reference voltage). The analog
input voltage range is between V_REFM to V_REFP. This means that V_REFM defines the minimum voltage and V_REFP
defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage
V_REFM of 1.5 V and the voltage V_REFP of 3.5 V (see also section Reference Voltage). The resulting analog input
voltage swing of 2 V can be expressed by:
VREFM v AINP v VREFP
(1)
VREFP
AINP
10-Bit
ADC
VREFM
Figure 33. Single-Ended Input Stage
A differential operation is desired for many applications due to better signal-to-noise ration. Figure 34 shows a
simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The differential
operation mode provides in terms of performance benefits over the single-ended mode and is therefore
recommended for best performance. The THS1009 offers 1 differential analog input and in the single-ended mode
2 analog inputs. If the analog input architecture is differential, common-mode noise and common-mode voltages can
be rejected. Additional details for both modes are given below.
AINP
AINM
VREFP
+
Σ ^VADC
–
10-Bit
ADC
VREFM
Figure 34. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, V_ADC, which is applied at the input
of the ADC is the difference between the input AINP and AINM. The voltage V_ADC can be calculated as follows:
VADC + ABS(AINP–AINM)
(2)
An advantage to single-ended operation is that the common-mode voltage
VCM
+
AINM
)
2
AINP
(3)
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND v AINM, AINP v AVDD
(4)
1 V v VCM v 4 V
(5)
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