THS1009_14 Datasheet, PDF (21/31 Pages) Texas Instruments – Simultaneous Sampling of Two Single-Ended Signals or One Differential Signals or Combination of Both

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THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
TIMING AND SIGNAL DESCRIPTION OF THE THS1009
The reading from the THS1009 and writing to the THS1009 is performed by using the chip select inputs (CS0, CS1),
the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This
is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two
chip select inputs can be used to interface easily to a processor.
Reading from the THS1009 takes place by an internal RD_int signal, which is generated from the logical combination
of the external signals CS0, CS1 and RD (see Figure 28). This signal is then used to strobe out the words and to
enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RD_int active while
the write input (WR) is inactive. The first of those external signals switching to its inactive state deactivates RD_int
again.
Writing to the THS1009 takes place by an internal WR_int signal, which is generated from the logical combination of
the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and 1. The
last external signal (either CS0, CS1 or WR) to become valid switches WR_int active while the read input (RD) is
inactive. The first of those external signals going to its inactive state deactivates WR_int again.
CS0
RDint
CS1
RD
WRint
WR
Data Bits
Control/Data
Registers
Figure 28. Logical Combination of CS0, CS1, RD, and WR
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