THS1009_14 Datasheet, PDF (16/31 Pages) Texas Instruments – Simultaneous Sampling of Two Single-Ended Signals or One Differential Signals or Combination of Both

THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
DIGITAL OUTPUT DATA FORMAT
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The digital output data format of the THS1009 can either be in binary format or in twos complement format. The
following tables list the digital outputs for the analog input voltages.
Table 2. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
AIN = (VREFP + VREFM)/2
AIN = VREFM
3FFh
200h
000h
Table 3. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
AIN = (VREFP + VREFM)/2
AIN = VREFM
1FFh
000h
200h
Table 4. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF
Vin = 0
Vin = –VREF
3FFh
200h
000h
Table 5. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF
Vin = 0
Vin = –VREF
1FFh
000h
200h
ADC CONTROL REGISTER
The THS1009 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired
mode. The bit definitions of both control registers are shown in Table 6.
REG
CR0
CR1
16
Table 6. Bit Definitions of Control Register CR0 and CR1
BIT 9
TEST1
RESERVED
BIT 8
TEST0
OFFSET
BIT 7
SCAN
BIN/2’s
BIT 6
DIFF1
R/W
BIT 5
DIFF0
RES
BIT 4
CHSEL1
RES
BIT 3
CHSEL0
RES
BIT 2
PD
RES
BIT 1
RES
SRST
BIT 0
VREF
RESET