THS1009_14 Datasheet, PDF (15/31 Pages) Texas Instruments – Simultaneous Sampling of Two Single-Ended Signals or One Differential Signals or Combination of Both

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THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
Figure 25 shows the timing of the conversion when one analog input channel is selected. The maximum throughput
rate is 8 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since this information
is not required for one analog input. There is a certain timing relationship required for the read signal with respect
to the conversion clock. This can be seen in Figure 26 and the timing specification. A more detailed description of
the timing is given in the section timing and signal description of the THS1009.
Sample N Sample N+1
Channel 1 Channel 1
Sample N+2 Sample N+3 Sample N+4
Channel 1
Channel 1 Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Sample N+7 Sample N+8
Channel 1 Channel 1
AIN
td(A)
tw(CONV_CLKH)
td(pipe)
tw(CONV_CLKL)
CONV_CLK
READ^†
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
Data N–4
Channel 1
Data N–3
Channel 1
Data N–2
Channel 1
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
†_{READ is the logical combination from CS0, CS1 and RD}
Figure 25. Conversion Timing in 1-Channel Operation
Figure 27 shows the conversion timing when two analog input channels are selected. The maximum throughput rate
per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data
is available to the data bus. This can be seen in Figure 26 and Table 2. A more detailed description of the timing is
given in the section timing and signal description of the THS1009.
Sample N
Channel 1, 2
AIN
td(A)
Sample N+1
Channel 1, 2
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
Sample N+2
Channel 1, 2
Sample N+3
Channel 1, 2
Sample N+4
Channel 1, 2
CONV_CLK
READ^†
SYNC
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-SYNCL)
tsu(CONV_CLKL-SYNCH)
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
†_{READ is the logical combination from CS0, CS1 and RD}
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Figure 26. Conversion Timing in 2-Channel Operation
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