LM3S2616 Datasheet, PDF (26/753 Pages) Texas Instruments – Stellaris® LM3S2616 Microcontroller

Revision History
Table 1. Revision History (continued)
Date
January 2011
Revision
9102
Description
■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ
to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.
■ Added "Reset Sources" table to System Control chapter.
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added note that specific module clocks must be enabled before that module's registers can be
programmed. There must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.
■ Changed I²C slave register base addresses and offsets to be relative to the I²C module base address
of 0x4002.0000 , so register bases and offsets were changed for all I²C slave registers. Note that
the hw_i2c.h file in the StellarisWare^® Driver Library uses a base address of 0x4002.0800 for the
I²C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that
StellarisWare uses the old slave base address for these offsets.
■ Corrected nonlinearity and offset error parameters (E_L, E_D and E_O) in ADC Characteristics table.
■ Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (V_NON parameter in Maximum Ratings table).
■ Additional minor data sheet clarifications and corrections.
September 2010
7783
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
■ Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control
and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the
Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register.
■ In the Internal Memory chapter:
– Added clarification of instruction execution during Flash operations.
– Deleted ROM Version (RMVER) register as it is not used.
■ In the GPIO chapter:
– Renamed the GPIO High-Speed Control (GPIOHSCTL) register to the GPIO High-Performance
Bus Control (GPIOHBCTL) register.
– Added clarification about the operation of the Advanced High-Performance Bus (AHB) and the
legacy Advanced Peripheral Bus (APB).
– Modified Figure 9-1 on page 351 and Figure 9-2 on page 352 to clarify operation of the GPIO
inputs when used as an alternate function.
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In Electrical Characteristics chapter:
– Added "Input voltage for a GPIO configured as an analog input" value to Table 22-1 on page 689.
– Added I_LKG parameter (GPIO input leakage current) to Table 22-4 on page 690.
– Corrected values for t_CLKRF parameter (SSIClk rise/fall time) in Table 22-20 on page 700.
■ Added dimensions for Tray and Tape and Reel shipping mediums.
26
November 17, 2011
Texas Instruments-Production Data