DDC114_14 Datasheet, PDF (26/37 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
POWER-UP SEQUENCING
Prior to power-up, all digital and analog inputs must be low.
After the power supplies have settled, release RESET
after time t₃₂. (See Figure 28 and Table 12.) Wait for time
t₃₃ to begin applying the digital signals CONV and CLK.
The first CONV pulse will complete the release state and
begin integration.
LAYOUT
POWER SUPPLIES AND GROUNDING
Both AVDD and DVDD should be as quiet as possible. It
is particularly important to eliminate noise from AVDD that
is non-synchronous with the DDC114 operation. Figure 27
illustrates two acceptable ways to supply power to the
DDC114. The first case shows two separate +5V supplies
for AVDD and DVDD. In this case, each +5V supply of the
DDC114 should be bypassed with 10µF solid tantalum
capacitors and 0.1µF ceramic capacitors. The second
case shows the DVDD power supply derived from the
AVDD supply with a < 10Ω isolation resistor. In both cases,
the 0.1µF capacitors should be placed as close to the
DDC114 package as possible. It is recommended that
both the analog and digital grounds (AGND and DGND) be
connected to a single ground plane on the printed circuit
board (PCB).
THERMAL PAD
It is strongly recommended that the thermal pad on the
DDC114 be connected to ground on the PCB. No PCB
traces should be routed underneath the thermal pad.
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VA
10µF
VD
10µF
AVDD
0.1µF
AGND
DDC114
DVDD
0.1µF
DGND
Separate Supplies
+5V
10µF
< 10Ω
0.1µF
AVDD AGND
DDC114
0.1µF
DVDD DGND
Single +5V Supply
Figure 27. Power-Supply Connection Options
SYMBOL
t₃₂
t₃₃
t₃₄
26
AVDD
DVDD
RESET
CONV
CLK
t₃₂
Release State
Start Integration
t₃₃
t₃₄
Integrate Side B
…
Figure 28. Timing Diagram at Power-Up of the DDC114
Table 12. Timing for the DDC114 Power-Up Sequence
DESCRIPTION
Power Supplies Settled to RESET Release
RESET Release to CONV, CLK Begin
First CONV Pulse Width
MIN
TYP
MAX
10
50
50
UNITS
ms
µs
µs