DDC114_14 Datasheet, PDF (19/37 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

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Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC114 remains
in those states until mbsy goes low, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 10, page 14). The top two
signals in Figure 16 are different CONV patterns that
produce the same state. This feature allows flexibility in
generating ncont mode CONV patterns. For example, the
DDC114 Evaluation Fixture operates in ncont mode by
generating a square wave with pulse width < t₆. Figure 17
illustrates operation in ncont mode using a 50% duty cycle
DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
CONV signal with T_INT = 512 CLK periods. Care must be
exercised when using a square wave to generate CONV.
There are certain integration times that must be avoided
since they produce very short intervals for state 2 (or state
7 if CONV is inverted). As seen in the state diagram, the
state progresses from 2 to 3 as soon as CONV is high. The
state machine does not insure that the duration of state 2
is long enough to properly prepare the next side for
integration (t₁₁). This must be done by the user with proper
timing of CONV. For example, if CONV is a square wave
with T_INT = 970 CLK periods, state 2 will only be 9 CLK
periods long; therefore, t₁₁ will not be met.
CONV1
CONV2
mbsy
State
3
4
1
23
4
1
2
Figure 16. Equivalent CONV Signals in Non-Continuous Mode
CONV
State
3
4
1
Integration
Status
mbsy
Int A Int B
2
3
4
1
Int A Int B
DVALID
Side A
Data
Side B
Data
Side A
Data
Figure 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal
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