DDC114_14 Datasheet, PDF (18/37 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
www.ti.com
Start Integration Side A
End Integration Side A
Start Integration Side B
End Integration Side B
Wait State
CONV
A/D Conversion
Input 1 and 2
A/D Conversion
Input 3 and 4
DVALID
T_INT
T_INT
t₁₂
t₁₃
t₁₆
t₁₂
t₁₅
Side A
Data Ready
Start Integration Side A
Release
State
t₁₇
Side B
Data Ready
Figure 14. Conversion Detail for the Internal Operation of Non-Continuous Mode
with Side A Integrated First
Table 8. Internal Timing for the DDC114 in Non-Continuous Mode
SYMBOL DESCRIPTION
T_INT
t₁₂
t₁₃
t₁₅
t₁₆
t₁₇
Integration Time (non-continuous mode)
A/D Conversion Time (internally controlled)
A/D Conversion Reset Time (internally controlled)
Integrator and A/D Conversion Reset Time
(internally controlled)
Total A/D Conversion and Reset Time (internally controlled)
Release Time
CLK = 4MHz, CLK_4X = 0
MIN
TYP
MAX
400
1,000,000
169.5
4
19.5
725.25 ± 0.25
18
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
MAX
UNITS
320
1,000,000 µs
141.25
µs
3.333
µs
16.25
µs
604.375 ± 0.208
µs
15
µs
Start Integration Side B
End Integration Side B
Start Integration Side A
End Integration Side A
Wait State
Start Integration Side B
Release
State
CONV
A/D Conversion
Inputs 1 and 2
A/D Conversion
Inputs 3 and 4
DVALID
T_INT
T_INT
t₁₂
t₁₃
t₁₆
t₁₂
t₁₅
Side B
Data Ready
t₁₇
Side A
Data Ready
Figure 15. Internal Operation Timing Diagram of Non-Continuous Mode with Side B Integrated First
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