AM3703 Datasheet, PDF (256/280 Pages) Texas Instruments – AM3715, AM3703 Sitara ARM Microprocessors

AM3715, AM3703
SPRS616F – JUNE 2010 – REVISED AUGUST 2011
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Table 6-123. MMC1 Interface Switching Characteristics—High-Speed MMC Mode^{(4) (8)}
NO.
PARAMETER
OPP100
MMC1
t_c(clk)
Frequency⁽¹⁾, output clk period
MMC2
t_W(clkH)
Typical pulse duration, output clk high
MMC2
t_W(clkL)
Typical pulse duration, output clk low
t_dc(clk)
t_J(clk)
Duty cycle error, output clk
Jitter standard deviation⁽³⁾, output clk
MMC1 Interface (1.8-V IO)
MIN
MAX
48
X⁽⁶⁾*PO⁽²⁾
Y⁽⁷⁾*PO⁽²⁾
1041.7
200
t_R(clk)
Rise time, output clk
t_F(clk)
Fall time, output clk
t_R(data)
Rise time, output data
t_F(data)
Fall time, output data
MMC5 t_d(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd
3.7
transition
3
3
3
3
14.1
MMC6
t_{d(CLKOH-DATx)} Delay time, mmc1_clk rising clock edge to
mmc1_dat[n:0]⁽⁵⁾ transition
3.7
14.1
MMC1 Interface (3.0-V IO)
t_R(clk)
Rise time, output clk
t_F(clk)
Fall time, output clk
t_R(data)
Rise time, output data
t_F(clk)
Fall time, output data
MMC5 t_d(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd
3.7
transition
3
3
3
3
14.1
MMC6
t_{d(CLKOH-DATx)} Delay time, mmc1_clk rising clock edge to
mmc1_dat[n:0]⁽⁵⁾ transition
3.7
14.1
(1) Related with the output clock maximum and minimum frequencies programmable in MMC module.
(2) PO = output clock period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) Corresponding figures showing timing parameters are common with the Standard MMC mode figures.
(5) In MMC1_dat[n:0], n is equal to 3.
(6) The X parameter is defined as follows:
OPP50
MIN
MAX
24
X⁽⁶⁾*PO⁽²⁾
Y⁽⁷⁾*PO⁽²⁾
2083.3
200
3
3
3
3
4.1
34.5
4.1
34.5
3
3
3
3
4.1
34.5
4.1
34.5
UNIT
MHz
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKD
1 or Even
Odd
X
0.5
(trunk[CLKD/2]+1)/CLKD
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
(7) The Y parameter is defined as follows:
CLKD
1 or Even
Odd
Y
0.5
(trunk[CLKD/2])/CLKD
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
(8) See Section 4.3.4, Processor Clocks.
256 Timing Requirements and Switching Characteristics
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