AM3703 Datasheet, PDF (239/280 Pages) Texas Instruments – AM3715, AM3703 Sitara ARM Microprocessors

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SPRS616F – JUNE 2010 – REVISED AUGUST 2011
Table 6-99. I²C Correspondence Standard vs Data Manual Timing References
TI
f_scl
t_w(sclH)
t_w(sclL)
t_{su(sdaV-sclH)}
t_h(sclH-sdaV)
t_{su(sdaL-sclH)}
t_h(sclH-sdaH)
t_{h(sclH-RSTART)}
t_w(sdaH)
STANDARD-I²C
Standard/Fast Modes
F_SCL
T_HIGH
T_LOW
T_SU;DAT
T_SU;DAT
T_SU;STA
T_HD;STA
T_SU;STO
T_BUF
High-Speed Mode
F_SCLH
T_HIGH
T_LOW
T_SU;DAT
T_SU;DAT
T_SU;STA
T_HD;STA
T_SU;STO
6.6.6 HDQ / 1-Wire Interface (HDQ/1-Wire)
NOTE
For more information, see HDQ/1-Wire / HDQ/1-Wire chapter of the AM/DM37x Multimedia
Device Technical Reference Manual (literature number SPRUGN4).
The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to
communicate between the master and the slave. The protocols employ an asynchronous return to one
mechanism where, after any command, the line is pulled high.
6.6.6.1 HDQ/1-Wire—HDQ Mode
Table 6-100 and Table 6-102 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-55 through Figure 6-59).
Table 6-100. HDQ Interface Read Timing
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
t_CYCH
t_HW1
t_HW0
t_RSPS
Read bit window timing
Read one data valid after HDQ low
Read zero data hold after HDQ low
Response time from HDQ slave device⁽¹⁾
190
32⁽²⁾
70⁽²⁾
190
250
μs
66⁽²⁾
μs
145⁽²⁾
μs
320
μs
(1) Defined by software
(2) If the HDQ slave device drives a logic-low state after t_HW0 max, it can be interpreted as a break pulse. For more information see
Table 6-101 and the HDQ/1-Wire chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4).
Table 6-101. HDQ Sampling Cases⁽¹⁾
CASES
FIRST SAMPLING (at 68 µs)
SECOND SAMPLING (at 180 µs)
1
L (logic-low state)
L (logic-low state)
2
L (logic-low state)
H (logic-high state)
3
H (logic-high state)
L (logic-low state)
4
H (logic-high state)
H (logic-high state)
(1) The different cases can be interpreted as follows:
– Case 1: If a logic-low state is present at the first sampling time and also at the second sampling time, the receive data can be
interpreted as a break pulse.
– Case 2: If a logic-low state is present at the first sampling time and a logic-high state is present at the second sampling time, the
receive data on the line is a zero (data).
– Case 3: Undefined.
– Case 4: If a logic-high state is present at the first sampling time and also at the second sampling time, the receive data on the line is
a one (data).
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Timing Requirements and Switching Characteristics 239
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