AM3703 Datasheet, PDF (247/280 Pages) Texas Instruments – AM3715, AM3703 Sitara ARM Microprocessors

AM3715, AM3703
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SPRS616F – JUNE 2010 – REVISED AUGUST 2011
Table 6-111. MMC1 Interface Switching Characteristics—SD Identification Modes^{(4) (7)} (continued)
NO.
PARAMETER
OPP100
OPP50
MIN
MAX
MIN
MAX
t_R(data)
Rise time, output data
10
10
t_F(data)
Fall time, output data
10
10
SD5 t_d(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd
6.3
2492.7
6.3
2492.7
transition
MMC1 Interface (3.0-V IO)
t_R(clk)
Rise time, output clock
10
10
t_F(clk)
Fall time, output clock
10
10
t_R(data)
Rise time, output data
10
10
t_F(data)
Fall time, output data
10
10
SD5 t_d(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd
6.3
2492.7
6.3
2492.7
transition
(1) Related with the output clock maximum and minimum frequencies programmable in mmc module.
(2) PO = output clock period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) Corresponding figures showing timing parameters are common with other interface modes. (See SD, HS SD modes).
(5) The X parameter is defined as follows:
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
CLKD
1 or Even
Odd
X
0.5
(trunk[CLKD/2]+1)/CLKD
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
(6) The Y parameter is defined as follows:
CLKD
1 or Even
Odd
Y
0.5
(trunk[CLKD/2])/CLKD
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
(7) See ^{Section 4.3.4}, Processor Clocks.
6.6.8.1.2 MMC1 Interface—High-Speed SD Mode
Table 6-113 and Table 6-114 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-65 and Figure 6-66).
Table 6-112. MMC1 Interface Timing Conditions—High-Speed SD Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Condition
C_LOAD
Output load capacitance⁽¹⁾
(1) Buffer strength configuration: SPEEDCTRL = 1.
VALUE
3
3
40
UNIT
ns
ns
pF
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Timing Requirements and Switching Characteristics 247
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