AM3703 Datasheet, PDF (253/280 Pages) Texas Instruments – AM3715, AM3703 Sitara ARM Microprocessors

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SPRS616F – JUNE 2010 – REVISED AUGUST 2011
Table 6-118. MMC1 Interface Timing Conditions—Standard MMC and MMC Identification Modes
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Conditions
C_LOAD
Output load capacitance⁽¹⁾
(1) Buffer strength configuration: SPEEDCTRL = 1.
VALUE
3
3
30
UNIT
ns
ns
pF
Table 6-119. MMC1 Interface Timing Requirements—Standard MMC and MMC Identification Modes^{(2) (3) (4)}
NO.
PARAMETER
OPP100
OPP50
MIN
MAX
MIN
MAX
MMC1 Interface (1.8-V IO)
MMC3 t_{su(CMDV-CLKIH)} Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
13.6
55.1
MMC4
MMC7
MMC8
t_{h(CLKIH-CMDIV)}
t_{su(DATxV-CLKIH)}
t_{h(CLKIH-DATxIV)}
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Setup time, mmc1_dat[n:0]⁽¹⁾ valid before mmc1_clk
rising clock edge
Hold time, mmc1_dat[n:0]⁽¹⁾ valid after mmc1_clk
rising clock edge
7.7
13.6
7.7
7.5
55.1
7.5
MMC1 Interface (3.0-V IO)
MMC3 t_{su(CMDV-CLKIH)} Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
13.6
55.1
MMC4
MMC7
MMC8
t_{h(CLKIH-CMDIV)}
t_{su(DATxV-CLKIH)}
t_{h(CLKIH-DATxIV)}
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Setup time, mmc1_dat[n:0]⁽¹⁾ valid before mmc1_clk
rising clock edge
Hold time, mmc1_dat[n:0]⁽¹⁾ valid after mmc1_clk
rising clock edge
7.7
13.6
7.7
7.5
55.1
7.5
(1) In mmc1_dat[n:0], n is equal to 3.
(2) Timing parameters are referred to output clock specified in Table 6-120.
(3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-120.
(4) See Section 4.3.4, Processor Clocks.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-120. MMC1 Interface Switching Characteristics—Standard MMC and MMC Identification Modes⁽⁷⁾
NO.
PARAMETER
MMC Identification Mode
MMC1 1/t_c(clk)
Frequency⁽¹⁾, output clk period
MMC2 t_W(clkH)
Typical pulse duration, output clk high
MMC2 t_W(clkL)
Typical pulse duration, output clk low
t_dc(clk)
t_J(clk)
Duty cycle error, output clk
Jitter standard deviation⁽³⁾, output clk
Standard MMC Identification Mode
MMC1 t_c(clk)
Frequency⁽¹⁾, output clk period
MMC2 t_W(clkH)
Typical pulse duration, output clk high
MMC2 t_W(clkL)
Typical pulse duration, output clk low
t_dc(clk)
t_J(clk)
Duty cycle error, output clk
Jitter standard deviation⁽³⁾, output clk
MMC1 Interface (1.8-V IO)
t_R(clk)
Rise time, output clk
OPP100
MIN
MAX
OPP50
MIN
MAX
UNIT
0.4
X⁽⁵⁾*PO⁽²⁾
Y⁽⁶⁾*PO⁽²⁾
125
200
0.4
X⁽⁵⁾*PO⁽²⁾
Y⁽⁶⁾*PO⁽²⁾
125
200
MHz
ns
ns
ns
ps
24
X⁽⁵⁾*PO⁽²⁾
Y⁽⁶⁾*PO⁽²⁾
2083.3
200
12
X⁽⁵⁾*PO⁽²⁾
Y⁽⁶⁾*PO⁽²⁾
4166.7
200
MHz
ns
ns
ps
ps
10
10
ns
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Timing Requirements and Switching Characteristics 253
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