TLC320AD77 Datasheet, PDF (25/33 Pages) Texas Instruments – 24-Bit 96 kHz Stereo Audio Codec

5 Application Information
5.1 Single-Ended to Differential External Analog Front-End Circuit
(f_s = 44.1 kHz)
A single-ended to differential external analog front-end example circuit is shown in Figure 5–1. It biases the
input signal around AV_DD/2 and applies the maximum input signal of 0.7 Vrms. The device sees a full-scale
differential input voltage of approximately 4 V_pp. For other maximum input signals, the ratio of R2/R1 can
be scaled accordingly to ensure a max ADC input of approximately 4 V_pp. As required by the ADC, R5, C4,
and R6 provide a single-pole low-pass antialiasing filter to attenuate unwanted frequencies. If the user
chooses to supply a single-ended input directly to the device (2 V_pp max), performance will be significantly
degraded.
Right Channel
Analog Input
0.7 Vrms
C1
21
1
R1
2
47 µF ^{10 kΩ}
AVDD/2
C2
12
10 pF
1 ^R2 2
10 kΩ
5V
U3:A
2_ ⁸
1
3+
4
GND
1 ^R3 2
10 kΩ
C3
12
10 pF
1 ^R4 2
10 kΩ
6
U3:B
_7
5+
1 ^R5 2
499 Ω
Antialiasing
Filter
1
2
C4
1000 pF
R6
1
2
499 Ω
AINRM
4 VPP
AINRP
Figure 5–1. Analog Front End (right channel) for 0.7 Vrms Input
5–1