TLC320AD77 Datasheet, PDF (21/33 Pages) Texas Instruments – 24-Bit 96 kHz Stereo Audio Codec

4 Parameter Measurement Information
MCLK
twH(MCLK)
twL(MCLK)
Figure 4–1. Master Clock Timing
SCLK
LRCK
td(LRCLK)
SDSODUINT^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtd(SÎÎÎÎÎÎDtsOuUÎÎÎÎÎÎ}_(STD) ^{ÎÎÎÎÎÎ}_IN) ^{ÎÎÎÎÎÎ}
th(SDIN)
Figure 4–2. Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing
SCLK
td(FS)
tw(FSHIGH)
LRCLK
SDOU^ÎÎÎT ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtd(SÎÎÎDOÎÎÎUT)ÎÎÎÎÎÎÎÎÎ}
SDI^ÎÎN ^{ÎÎÎÎÎÎÎÎÎÎÎÎtsuÎÎ(SDIÎÎN) ÎÎÎÎ}
th(SDIN)
Figure 4–3. DSP Serial Port Timing
4–1