TLC320AD77 Datasheet, PDF (15/33 Pages) Texas Instruments – 24-Bit 96 kHz Stereo Audio Codec

2.14.4 DSP Compatible Serial Interface Format
SCLK
LRCLK = fs
SDIN
15 14 13
0 15 14 13
0
SDOUT
15 14 13
0 15 14 13
0
Left Channel
(MSB = 15)
Right Channel
(MSB = 15)
Figure 2–4. DSP Compatible Serial Interface Format (for 16-bits)
Note the following characteristics of this protocol.
• MCLK = 256 F_s only
• SCLK = 64 times the sampling frequency.
• Serial data is sampled with the falling edge of SCLK.
• Serial data is transmitted on the rising edge of SCLK.
2.15 Sampling Frequency Ranges
The TLC320AD77C supports two sampling frequency ranges.
• When in the normal option ranging from 16 kHz up to 48 kHz, SPDMOD = low is used.
• When in the fast option ranging from greater than 48 kHz up to 96 kHz, SPDMOD = high is used.
NOTE:
The high speed clocks should never be applied while SPDMOD is low in order to
avoid glitches in the DAC and ADC outputs.
Table 2–1. Example Master Clock Frequency Rates
SAMPLING RATE FREQUENCY
(kHz)
32
MCLK FREQUENCY
256 fs
384 fs
8.192 MHz 12.2880 MHz
SPDMODE
0
44.1
11.2896 MHz 16.9340 MHz
0
48
12.2880 MHz 18.432 MHz
0
64
16.384 MHz 24.576 MHz
1
88.2
22.579 MHz 33.868 MHz
1
96
24.576 MHz 36.864 MHz
1
2.16 Power Sequences
2.16.1 Initial Power Up
For initial power up, the ADC and DAC outputs are valid after the 150 ms settling time required for the analog
stages. Holding the power down pin low while ramping up the power supplies is recommended to avoid
glitches in the DAC output.
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