DDC112_15 Datasheet, PDF (25/34 Pages) Texas Instruments – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

CONV
T_INT
T_INT
DVALID
DXMIT
t₃₀
t₃₁
T_INT
T_INT
DCLK
•••
•••
DOUT
•••
Side A
Data
•••
Side B
Data
SYMBOL
t₃₀
t₃₁
DESCRIPTION
1st Ncont Mode Data Ready (see SBAA024)
2nd Ncont Mode Data Ready (see SBAA024)
FIGURE 27. Readback in Noncontinuous Mode.
CLK = 10MHz
MIN
TYP
MAX
421.1 ±0.3
454.8
CLK = 15MHz
MIN
TYP
MAX
280.8
303.2
UNITS
µs
µs
CONV
(HIGH at power-up)
CONV
(LOW at power-up)
Release State
Power-Up
Initialization
Start
Integration
t₃₂
t₃₃
Integrate Side A
Integrate Side B
Power Supplies
FIGURE 28. Timing Diagram at Power-Up of the DDC112.
SYMBOL
t₃₂
t₃₃
DESCRIPTION
Power-On Initialization Period
From Release Edge to Integration Start
TABLE XI. Timing for the DDC112 Power-Up Sequence.
LAYOUT
Power Supplies and Grounding
Both AV_DD and DV_DD should be as quiet as possible. It is
particularly important to eliminate noise from AV_DD that is
non-synchronous with the DDC112 operation. Figure 29
illustrates two acceptable ways to supply power to the
DDC112. The first case shows two separate +5V supplies for
AV_DD and DV_DD. In this case, each +5V supply of the
DDC112 should be bypassed with 10µF solid tantalum ca-
pacitors and 0.1µF ceramic capacitors. The second case
MIN
TYP
MAX
UNITS
50
µs
50
µs
shows the DV_DD power supply derived from the AV_DD supply
with a < 10Ω isolation resistor. In both cases, the 0.1µF
capacitors should be placed as close to the DDC112 pack-
age as possible.
Shielding Analog Signal Paths
As with any precision circuit, careful printed circuit layout will
ensure the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—
particularly at the analog input pins. Digital signals should be
kept as far from the analog input signals as possible on the
PC board.
DDC112
25
SBAS085B
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