DDC112_15 Datasheet, PDF (18/34 Pages) Texas Instruments – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC112 remains in
those states until mbsy goes LOW, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 9). The top two signals are
different CONV patterns that produce the same state.
This feature can be a little confusing at first, but it does allow
flexibility in generating ncont mode CONV patterns. For
example, the DDC112 Evaluation Fixture operates in the
ncont mode by generating a square wave with pulse width
< t₆. Figure 17 illustrates operation in the ncont mode using
a 50% duty cycle CONV signal with T_INT = 1620 CLK
periods. Care must be exercised when using a square wave
to generate CONV. There are certain integration times that
must be avoided since they produce very short intervals for
state 2 (or state 7 if CONV is inverted). As seen in the state
diagram, the state progresses from 2 to 3 as soon as CONV
is HIGH. The state machine does not insure that the duration
of state 2 is long enough to properly prepare the next side
for integration (t₁₁). This must be done by the user with
proper timing of CONV. For example, if CONV is a square
wave with T_INT = 3042 CLK periods, state 2 will only be 18
CLK periods long, therefore, t₁₁ will not be met.
CONV1
CONV2
mbsy
State
3
4
1
23
4
FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.
1
2
CONV
State
3
4
1
Integration
Status
mbsy
Int A Int B
DVALID
Side A
Data
2
3
4
Int A Int B
Side B
Data
FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.
1
Side A
Data
18
DDC112
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