DDC112_15 Datasheet, PDF (14/34 Pages) Texas Instruments – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration. Con-
sequently, keeping track of the current status of CONV is all
that is needed to know the current state. Cont mode opera-
tion corresponds to states 3-6. Two of the states, 3 and 6,
only perform an integration (no m/r/az cycle).
mbsy becomes important when operating in the ncont mode;
states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy
is active, the DDC112 will enter or remain in either ncont
state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for integra-
tion. As mentioned above, in the ncont states, the inputs to
the DDC112 are grounded.
One interesting observation from the state diagram is that the
integrations always alternate between sides A and B. This
relationship holds for any CONV pattern and is independent
of the mode. States 2 and 7 insure this relationship during the
ncont mode.
When power is first applied to the DDC112, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held HIGH at power-up, the beginning state is 1.
Conversely, for CONV held LOW at power-up, the beginning
state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6, and 4-5. Inverting
CONV results in the states progressing through their sym-
metrical match.
TIMING EXAMPLES
Cont Mode
A few timing diagrams will now be discussed to help illustrate
the operation of the state machine. These are shown in
Figures 10 through 19. Table V gives generalized timing
specifications in units of CLK periods. Values in µs for
Table V can be easily found for a given CLK. For example,
if CLK = 10MHz, then a CLK period = 0.1µs. t₆ in Table V
would then be 479.4µs.
SYMBOL DESCRIPTION
VALUE (CLK periods)
t₆
Cont mode m/r/az cycle.
4794
t₇
Cont mode data ready.
4212
(t_INT > 4794)
4212 ±3 (t_INT = 4794)
t₈
1st ncont mode data ready.
4212 ±3
t₉
2nd ncont mode data ready. 4548
t₁₀
Ncont mode m/r/az cycle.
9108
TABLE V. Timing Specifications Generalized in CLK Periods.
Figure 10 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal is
CONV and is supplied by the user. The next line indicates the
current state in the state diagram. The following two traces
show when integrations and measurement cycles are under-
way. The internal signal mbsy is shown next. Finally, DVALID
is given. As described in the data sheet, DVALID goes active
LOW when data is ready to be retrieved from the DDC112.
It stays LOW until DXMIT is taken LOW by the user. In Figure
10 and the following timing diagrams, it is assumed that
DXMIT it taken LOW soon after DVALID goes LOW. The text
below the DVALID pulse indicates the side of the data and
arrows help match the data to the corresponding integration.
The signals shown in Figures 10 through 19 are drawn at
approximately the same scale.
In Figure 10, the first state is ncont state 1. The DDC112
always powers up in the ncont mode. In this case, the first
state is 1 because CONV is initially HIGH. After the first two
states, cont mode operation is reached and the states begin
toggling between 4 and 5. From now on, the input is being
continuously integrated, either by side A or side B. The time
needed for the m/r/az cycle, t₆, is the same time that
CONV
State 1
2
Integration
Status
m/r/az
Status
mbsy
3
Integrate A
4
Integrate B
m/r/az A
t₆
5
Integrate A
m/r/az B
4
Integrate B
m/r/az A
DVALID
t=0
Power-Up
SYMBOL
t₆
t₇
DESCRIPTION
Cont mode m/r/az cycle.
Cont mode data ready.
t₇
Side A
Data
VALUE (CLK = 10MHz)
479.4µs
421.2µs
421.2 ±0.3µs
(T_INT > 479.4µs)
(T_INT = 479.4µs)
FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up).
Side B
Data
Side A
Data
VALUE (CLK = 15MHz)
319.6µs
280.8µs
280.8 ±0.2µs
(T_INT > 319.6µs)
(T_INT = 319.6µs)
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DDC112
SBAS085B