TLC5943_17 Datasheet, PDF (24/40 Pages) Texas Instruments – 16-Channel, 16-Bit PWM LED Driver with 7-Bit Global Brightness Control

TLC5943
SBVS101 – DECEMBER 2007
www.ti.com
Grayscale (GS) Shift Register and Data Latch
The Grayscale (GS) Shift Register and data latch 1 and 2 are each 256 bits in length, and set the PWM timing
for each constant current driver. See Table 4 for the ON time duty of each GS data bit. Figure 28 shows the shift
register and latch configuration. Refer to Figure 11 for the timing diagram for writing data into the GS shift
register and latch.
The driver on time is controlled by the data in the GS second data latch. GS data can be set into the latch by the
rising edge of XLAT with BCSEL = low after writing data into the GS shift register with SIN and GSCLK with
BCSEL = low. A BCSEL level change occurs during SCLK = low, and after 100 ns from the rising edge of XLAT.
When the device powers up, the data in the GS shift register and latches are not set to any default value.
Therefore, GS data must be written to the GS latch before turning on the constant current output. Also, BLANK
should be at a high level when powering on the device, because the constant current may be turned on as well.
All constant current output is off when BLANK is at a high level.
GS Data for OUT15
MSB
255
GS Data
for Bit 15
of OUT15
¼
240
GS Data
for Bit 0
of OUT15
239
GS Data
for Bit 15
of OUT14
16
GS Data
¼
for Bit 0
of OUT1
Grayscale Shift Register (16 Bits x 16 Channels)
GS Data for OUT0
15
GS Data
for Bit 15
of OUT0
¼
LSB
0
GS Data
for Bit 0
of OUT0
SIN with
BCSEL = low
SCLK with
BCSEL = low
¼
¼
¼
GS Data for OUT15
MSB
255
GS Data
for Bit 15
of OUT15
¼
240
GS Data
for Bit 0
of OUT15
¼ GS Data for OUT14 GS Data for OUT1
239
GS Data
for Bit 15
of OUT14
16
GS Data
¼
for Bit 0
of OUT1
Grayscale Data Latch 1 (16 Bits x 16 Channels)
GS Data for OUT0
15
GS Data
for Bit 15
of OUT0
¼
LSB
0
GS Data
for Bit 0
of OUT0
XLAT with
BCSEL = low
¼
¼
¼
GS Data for OUT15
MSB
255
GS Data
for Bit 15
of OUT15
¼
240
GS Data
for Bit 0
of OUT15
GS Data for OUT14 GS Data for OUT1
¼
239
GS Data
for Bit 15
of OUT14
16
GS Data
¼
for Bit 0
of OUT1
Grayscale Data Latch 2 (16 Bits x 16 Channels)
GS Data for OUT0
15
GS Data
for Bit 15
of OUT0
¼
LSB
0
GS Data
for Bit 0
of OUT0
256 Bits
To PWM Timing Control Block
Figure 28. Grayscale Shift Register and Data Latch Configuration
65,536th GSCLK
when Auto Repeat is
enabled or Blank
with BCSEL = low
24
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