TLC5943_17 Datasheet, PDF (12/40 Pages) Texas Instruments – 16-Channel, 16-Bit PWM LED Driver with 7-Bit Global Brightness Control

TLC5943
SBVS101 – DECEMBER 2007
www.ti.com
BCSEL
T_SU3
T_SU4
T_H3
SIN N/A
BC BC BC BC BC BC BC
7B 6B 5B 4B 3B 2B 1B
BC
0B
BC BC BC BC BC BC BC
BC
7C 6C 5C 4C 3C 2C 1C
0C
T_H0
T_SU0
T_WH0
T_SU1
T_H2
SCLK
XLAT
12 3 4 5 6 7 8
T_WL0
T_H1
12 3 4 5 6 7 8
T_WH1
Latched Data
for Brightness Control
(Internal)
SOUT
Previous Data
New BC Data
t_D0
BC BC BC BC BC BC BC BC
BC
BC BC BC BC BC BC BC
BC
7A 6A 5A 4A 3A 2A 1A 0A
7B
6B 5B 4B 3B 2B 1B 0B
7C
t_R0/t_F0
Figure 12. Brightness Control Data Write Timing
BCSEL
Low ('L') level
The SCLK falling edge must be prior to the XLAT rising edge in case SID is read.
SIN
GS0
1A
GS0
0A
GS15 GS15 GS15 GS15 GS15
15B 14B 13B 12B 11B
GS15 GS15 GS15 GS14 GS14 GS14 GS14
2B
1B
0B 15B 14B 13B 12B
GS0
1B
GS0
0B
SCLK
XLAT
SOUT
255 256
T_SU1
1
2
3
4
5 13 14 15 16 17 18 19 20 254 255 256
T_H1 T_WH1 T_SU5
GS0
0
GS15
15A
t_D0
LOD
15
256
LOD
14
255
LOD
13
254
LOD
12
253
LOD
3
244
LOD
2
243
LOD
1
242
LOD
0
TEF
GS14 GS14
14A 13A
241
239 238
GS0
1A
2
GS0
0A
1
GS15
15B
SID are entered in the GS shift register at the first rising edge of SCLK after XLAT goes low.
The SID readout consists of the saved LOD result at the 33rd GSCLK rising edge in the previous display period
and the TEF data after the previous TEF data readout.
Figure 13. Status Information Data Read Timing
12
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