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TMS320DM6467T
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7.12.4 Transport Stream Interface (TSIF) Electrical Data/Timing
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-52. Timing Requirements for TSIF Input (see Figure 7-45)
NO.
1
t_c(TSCLKIN)
2
t_w(TSCLKIN)
3
t_t(TSCLKIN)
4
t_{su(TSDATAIN-TSCLKINV)}
5
t_{h(TSCLKINV-TSDATAIN)}
Cycle time, TSx_CLKIN
Pulse duration, TSx_CLKIN high/low⁽²⁾
Transition time, TSx_CLKIN
Setup time, TSx_CTL/TSx_DATA⁽⁴⁾ input valid
before TSx_CLKIN edge
All Others
TSx_WAIT
IN
Hold time, TSx_CTL/TSx_DATA⁽⁴⁾ input valid after
TSx_CLKIN edge
-1G
SERIAL
INPUT
PARALLEL
INPUT ⁽¹⁾
MIN MAX MIN MAX
10
16.7
0.4C
0.4C
3 ⁽³⁾
3 ⁽³⁾
4
4
UNIT
ns
ns
ns
ns
13
13
ns
0
0
ns
(1) TSIF1 supports SERIAL INPUT mode only.
(2) C = TSx_CLKIN period (cycle time) in ns.
(3) For a 4-inch transmission line with 4-pF load capacitance at the device pin.
(4) TSx_CTL/TSx_DATA input includes: TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0] for a parallel input. For a serial
input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and TS0_DIN7 or TS1_DIN.
1
TSx_CLKIN
(Positive Edge Clocking)
2
3
2
3
TSx_CLKIN
(Negative Edge Clocking)
4
5
TSx_CTL/
TSx_DATA^(A)
A. TSx_CTL/TSx_DATA input includes: TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0] for a parallel
input. For a serial input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and
TS0_DIN7 or TS1_DIN.
Figure 7-45. TSIF Input Timing
Table 7-53. Switching Characteristics Over Recommended Operating Conditions for TSIF Output
(see Figure 7-46)
NO.
6
t_c(TSCLKO)
7
t_w(TSCLKO)
8
t_t(TSCLKO)
Cycle time, TSx_CLKO
Pulse duration, TSx_CLKO high/low⁽²⁾
Transition time, TSx_CLKO
-1G
SERIAL
OUTPUT
PARALLEL
OUTPUT ⁽¹⁾
MIN MAX MIN MAX
10
16.7
0.4C
0.4C
3 ⁽³⁾
3 ⁽³⁾
UNIT
ns
ns
ns
(1) TSIF1 supports SERIAL OUTPUT mode only.
(2) C = TSx_CLKO period (cycle time) in ns.
(3) For a 4-inch transmission line with 4-pF load capacitance at the device pin.
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Peripheral Information and Electrical Specifications 235
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