TMS320DM6467T Datasheet, PDF (110/352 Pages) Texas Instruments – TMS320DM6467T Digital Media System-on-Chip

TMS320DM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
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4.7 Multiplexed Pin Configurations
DM6467T makes extensive use of pin multiplexing to accommodate a large number of peripheral function
in the smallest possible package, providing the ultimate flexibility for end applications.
The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsiblie for controlling
all pin multiplexing functions on the DM6467T. The default setting of some of the PINMUX0 and PINMUX1
bit fields are configured by configuration pins latched at reset (see Section 4.5.1, Device and Peripheral
Configurations at Device Reset). After reset, software may program the PINMUX0 and PINMUX1 registers
to switch pin functionalities.
The following peripherals have multiplexed pins: VPIF, TSIF0, TSIF1, CRGEN0, CRGEN1, EMIFA, PCI,
HPI, ATA, PWM0, PWM1, UART0, UART1, UART2, Audio Clock Selector, the USB USB_DRVVBUS pin,
and GPIO.
4.7.1 Pin Muxing Selection At Reset
This section summarizes pin mux selection at reset.
The configuration pins CS2BW and PCIEN, latched at device reset, determine the default pin muxing. For
more details on the default pin muxing at reset, see Section 4.5, Configurations At Reset.
4.7.2 Pin Muxing Selection After Reset
The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions.
Some pin functions require a combination of PINMUX0/PINMUX1 bit fields. For more details on the
combination of the PINMUX bit fields that control each muxed pin, see Section 4.7.3, Pin Multiplexing
Details.
This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed
discussion on how to program each Pin Mux Block, see Section 4.7.3, Pin Multiplexing Details.
4.7.2.1 PINMUX0 Register Description
The Pin Multiplexing 0 Register controls the pin function in the EMIFA/ATA/HPI/PCI, TSIF0, TSIF1,
CRGEN, Block. The PINMUX0 register format is shown in Figure 4-18 and the bit field descriptions are
given in Table 4-22. Some muxed pins are controlled by more than one PINMUX bit field. For the
combination of the PINMUX bit fields that control each muxed pin, see Section 4.7.3, Pin Multiplexing
Details. For more information on the block pin muxing and pin-by-pin muxing control, see specific block
muxing section (for example, for CRGEN Pin Mux Control, see Section 4.7.3.7, CRGEN Signal Muxing).
31
30
29
28
27
VBUSDIS STCCK AUDCK1 AUDCK0 RSV
R/W-0 R/W-0 R/W-0 R/W-0 R-0
26
24
CRGMUX
R/W-000
23
22
TSSOMUX
R/W-00
21
20
TSSIMUX
R/W-00
19
18
TSPOMUX
R/W-00
17
16
TSPIMUX
R/W-00
15
RESERVED
R-0000 0000 00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
6
5
4
3
2
1
0
RSV
RESERVED
PCIEN HPIEN ATAEN
R/W-0
R-0
R/W-L R/W-0 R/W-0
Figure 4-18. PINMUX0 Register [0x01C4 0000]
110 Device Configurations
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